LTC6802-2 Multicell Addressable Battery Stack Monitor Features n n n n n n n n n n n n n Description Measures Up to 12 Li-Ion Cells in Series (60V Max) Stackable Architecture Enables Monitoring High Voltage Battery Stacks Individually Addressable with 4-Bit Address 0.
LTC6802-2 Absolute Maximum Ratings Pin Configuration (Note 1) TOP VIEW Total Supply Voltage (V+ to V–)..................................60V Input Voltage (Relative to V–) C1............................................................. –0.3V to 9V C12...........................................V+ – 0.6V to V+ + 0.3V Cn (Note 5).......................... –0.3V to Min (9 • n, 60V) Sn (Note 5).......................... –0.3V to Min (9 • n, 60V) All Other Pins............................................ –0.
LTC6802-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications VACC VERR Measurement Resolution Quantization of the ADC l ADC Offset Voltage (Note 2) l –0.5 0.5 mV ADC Gain Error (Note 2) l –0.12 –0.22 0.12 0.22 % % Total Measurement Error (Note 4) VCELL = 0V VCELL = 2.
LTC6802-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
LTC6802-2 Typical Performance Characteristics Cell Measurement Total Unadjusted Error vs Input Resistance Cell Measurement Total Unadjusted Error 2 0 –2 –4 –6 –8 –10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V) 68022 G09 –20 –30 –40 RS = 1k RS = 2k RS = 5k RS = 10k –60 RS IN SERIES WITH Cn AND Cn – 1 –70 NO EXTERNAL CAPACITANCE ON Cn AND Cn – 1 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
LTC6802-2 Typical Performance Characteristics Supply Current vs Supply Voltage Standby Cell Input Bias Current During Conversion CELL INPUT = 3.6V STANDBY SUPPLY CURRENT (µA) C PIN BIAS CURRENT (µA) 2.65 2.60 2.55 2.50 2.45 2.40 2.35 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 60 0.90 50 0.85 40 30 20 0 10 20 30 40 SUPPLY VOLTAGE (V) 50 1 0 –1 –2 –3 –4 –5 –50 0.60 60 DEVICE IN STANDBY PRIOR TO MAKING DIE MEASUREMENTS TO MINIMIZE SELF HEATING –25 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 5 3.
LTC6802-2 Typical Performance Characteristics TA = –40°C 4.5 TA = 25°C 4.0 3.5 3.0 NO EXTERNAL LOAD ON VREG, CDC = 2 (CONTINUOUS CELL CONVERSIONS) 5 15 TA = –45°C TA = 25°C TA = 85°C TA = 105°C 45 TA = 85°C 5.0 VREG (V) 50 DISCHARGE RESISTANCE (Ω) 5.5 Internal Discharge Resistance vs Cell Voltage VREG Line Regulation 25 35 45 SUPPLY VOLTAGE (V) 40 35 30 25 20 15 10 5 0 55 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
LTC6802-2 Pin Functions V+ (Pin 1): Tie Pin 1 to the most positive potential in the battery stack. V+ must be approximately the same potential as C12. C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1 through C12 are the inputs for monitoring battery cell voltages. Up to 12 cells can be monitored. The lowest potential is tied to the V– pin. The next lowest potential is tied to C1 and so forth.
LTC6802-2 Pin Functions pin becomes high impedance. Either a “1” or a “0” is read back, depending on the voltage present at Pin 35. The GPIOs make it possible to turn on/off circuitry around the LTC6802-2, or read logic values from a circuit around the LTC6802-2. When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See Monitor Mode in the Applications Information section. A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs.
LTC6802-2 TIMING Diagram Timing Diagram of the Serial Interface t4 t1 t2 t6 t3 t7 SCKI D3 SDI D2 D1 D7 … D4 D0 D3 t5 CSBI t8 SDO D4 D3 D2 PREVIOUS COMMAND D1 D0 D7 … D4 CURRENT COMMAND D3 68022 TD Operation Theory of operation The LTC6802-2 is a data acquisition IC capable of measuring the voltage of 12 series connected battery cells. An input multiplexer connects the batteries to a 12-bit delta-sigma analog to digital converter (ADC).
LTC6802-2 Operation IC #3 TO IC #7 + + + + + + + + + + + LTC6802-2 IC #2 V+ CSBI C12 SDO S12 SDI C11 SCKI S11 A3 C10 A2 S10 A1 C9 A0 S9 GPIO2 C8 GPIO1 S8 WDTB C7 MMB S7 TOS C6 VREG VREF S6 VTEMP2 C5 VTEMP1 S5 NC C4 V– S4 S1 C3 C1 S3 S2 C2 V2– OE2 BATTERY POSITIVE 350V V1– OE1 + V2– V1– V2+ V1+ DIGITAL ISOLATOR ADDRESS 1 + 3V + + + + + + + + + + + + + + + + + + + + + LTC6802-2 IC #8 V+ CSBI C12 SDO S12 SDI C11 SCKI S11 A3 C10 A2 S10 A1 C9 A0 S9 GPIO2 C8 GPIO1 S8 WDTB C7 MMB S7 TOS C6 VREG VREF S
LTC6802-2 Operation 4. Issue a RDCV command and store all cell measurements into array CELLB(n). LTC6802-2 B4 B3 C4 + 5. For each value of n from 1 to 11: If CELLB(n + 1) – CELLA(n + 1) ≥ +200mV, C3 + MUX C2 + then Cn is open, otherwise it is not open. C1 + V– 100µA 68022 F02 Figure 2. Open Connection LTC6802-2 + B4 B3 + + + + C4 CF4 CF3 C3 C2 MUX C1 V– 100µA 68022 F03 Figure 3. Open Connection with RC Filtering B4 measurement when C3 is open.
LTC6802-2 Operation Discharging During Cell Measurements The primary cell voltage A/D measurement commands (STCVAD and STOWAD) automatically turn off a cell’s discharge switch while its voltage is being measured. The discharge switches for the cell above and the cell below will also be turned off during the measurement. For example, discharge switches S4, S5, and S6 will be disabled while cell 5 is being measured.
LTC6802-2 Applications Information Using the LTC6802-2 with Less Than 12 Cells The LTC6802-2 can typically be used with as few as 4 cells. The minimum number of cells is governed by the supply voltage requirements of the LTC6802-2. The sum of the cell voltages must be 10V to guarantee that all electrical specifications are met. Figure 5 shows an example of the LTC6802-2 when used to monitor 7 cells. The lowest C inputs connect to the 7 cells and the upper C inputs connect to V+. Other configurations, e.g.
LTC6802-2 Applications Information Modes of Operation The LTC6802-2 has three modes of operation: standby, measure and monitor. Standby mode is a power saving state where all circuits except the serial interface are turned off. In measure mode, the LTC6802-2 is used to measure cell voltages and store the results in memory. Measure mode will also monitor each cell voltage for overvoltage (OV) and undervoltage (UV) conditions. In monitor mode, the device will only monitor cells for UV and OV conditions.
LTC6802-2 Applications Information Table 1. Monitor Mode Cell Selection WDTB GPIO2 GPIO1 CELL INPUTS MONITORED 0 0 0 Cells 1 to 5 0 0 1 Cells 1 to 6 0 1 0 Cells 1 to 7 0 1 1 Cells 1 to 8 1 0 0 Cells 1 to 9 1 0 1 Cells 1 to 10 1 1 0 Cells 1 to 11 1 1 1 Cells 1 to 12 If MMB is low then brought high, all device configuration values are reset to the default states including the VUV, VOV, and CDC configuration bits.
LTC6802-2 Applications Information CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) SDO MSB (DATA) LSB (DATA) 68022 F07 Figure 7. Transmission Format (Read) CSBI SCKI SDI MSB (CMD) BIT6 (CMD) SDO LSB (CMD) POLL STATE 68022 F08 Figure 8. Transmission Format (Poll) With broadcast commands all devices can be sent commands simultaneously. This is useful for A/D conversion and polling commands. It can also be used with write commands when all parts are being written with the same data.
LTC6802-2 Applications Information is enabled when the LVLPL bit is low. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data out will be low when any device is busy performing an A/D conversion and will toggle at 1kHz when no device is busy.
LTC6802-2 Applications Information Table 2. Protocol Key PEC Packet error code (CRC-8) Master-to-slave N Number of bits Slave-to-master … Continuation of protocol Complete byte of data Table 3. Broadcast Poll Command 8 Command Poll Data Table 4. Broadcast Read 8 8 Command Data Byte Low 8 8 … Data Byte High PEC … Data Byte High Table 5. Broadcast Write 8 8 Command Data Byte Low 8 Table 6. Address Poll Command 4 4 8 1000 Address Command Poll Data Table 7.
LTC6802-2 Applications Information Commands Table 9.
LTC6802-2 Applications Information Memory Map Table 10 through Table 15 show the memory map for the LTC6802-2. Table 15 gives bit descriptions. Table 10.
LTC6802-2 Applications Information Table 12. Flag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FLGR0 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C10OV C10UV C9OV C9UV *Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high. Table 13.
LTC6802-2 Applications Information Table 15.
LTC6802-2 Applications Information Serial Command Example for LTC6802-2 (Addressable Configuration) Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T) Write Configuration Registers (Broadcast Command) 1. 2. 3. 4.
LTC6802-2 Applications Information Poll Interrupt Status (Level Polling) 1. 2. 3. 4. 5. 6. Pull CSBI low Send Address byte for bottom device Send PLINT command byte SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high Pull CSBI high to exit polling Repeat steps 1-5 for middle device and top device Fault Protection Overview Care should always be taken when using high energy sources such as batteries.
LTC6802-2 Applications Information Internal Protection Diodes Each pin of the LTC6802-2 has protection diodes to help prevent damage to the internal device structures caused by external application of voltages beyond the supply rails as shown in Figure 9. The diodes shown are conventional silicon diodes with a forward breakdown voltage of 0.5V. The unlabeled Zener diode structures have a reverse-breakdown characteristic which initially breaks down at 12V then snaps back to a 7V clamping potential.
LTC6802-2 Applications Information No resistor should be placed in series with the V– pin. Because the supply current flows from the V– pin, any resistance on this pin could generate a significant conversion error for CELL1. Reading External temperature probes Using Dedicated Inputs The LTC6802-2 includes two channels of ADC input, VTEMP1 and VTEMP2, that are intended to monitor thermistors (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array.
LTC6802-2 Applications Information total stack potential. This provides a redundant operational measurement of the cells in the event of a malfunction in the normal acquisition process, or as a faster means of monitoring the entire stack potential. Figure 15 shows a means of providing both of these features. A resistor divider is used to provide a low voltage representation of the full stack potential (C12 to C0 voltage) with MOSFETs that decouple the divider current under unneeded conditions.
LTC6802-2 Applications Information PCB LAYOUT CONSIDERATIONS Providing High speed opto-isolation of the SPI data port Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6802-2 require more power on the isolated (battery) side than can be furnished by the VREG output of the LTC6802-2. To keep battery drain minimal, this means that a DC/DC function must be implemented along with a suitable data isolation circuit, such as shown in Figure 16.
LTC6802-2 Applications Information 43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 25.2V 25.2V 21.6V 21.6V 18V 18V 14.4V 14.4V 10.8V 10.8V 7.2V V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 LTC6802-2 CSBI SDO SDI SCKI A3 A2 A1 A0 GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V– S1 C1 S2 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 5.5V 3.1V 1.5V 1.5V 0V 0V 3.
LTC6802-2 Applications Information Converter Details The LTC6802-2’s ADC has a second-order delta-sigma modulator followed by a Sinc2, finite impulse response (FIR) digital filter. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A simple 16kHz, 1-pole filter composed of a 100Ω resistor and a 0.1μF capacitor at each input will provide adequate filtering for most applications. These component values will not degrade the DC accuracy of the ADC.
LTC6802-2 Package Description G Package 44-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1754 Rev Ø) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 7.8 – 8.2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 5.3 – 5.7 0.25 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 – 5.60* (.197 – .221) PARTING LINE 0.10 – 0.25 (.004 – .010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2.0 (.079) MAX 1.65 – 1.85 (.065 – .073) 0° – 8° 0.
LTC6802-2 Revision History REV DATE DESCRIPTION PAGE NUMBER A 01/10 Additions to Absolute Maximum Ratings Changes to Electrical Characteristics Change to Graph G10 Text Changes to Pin Functions Replaced Open-Connection Detection Section Edits to Figures 1, 9 Text Changes to Operation Section Text Changes to Applications Information Section Edits to Tables 4, 5, 9, 10, 15, 16 2 3, 4 5 8, 9 10, 11, 12 11, 26 13 14, 25, 27 19, 20, 21, 23 68022fa Information furnished by Linear Technology Corporation i
LTC6802-2 Typical Application Stacked Daisy-Chain SPI Bus for LTC6802-2 VBATT LTC6802-2 IC #3 VREG 1M 1.8k WDT 2.2k 2.2k 2.2k NDC7002N ALL NPN: CMPT8099 ALL PNP: CMPT8599 ALL PN: RS07J ALL SCHOTTKY: CMD5H2-3 SDI SCKI CSBI SDO V− LTC6802-2 IC #2 VREG 100Ω 2.2k 2.2k 2.2k 100Ω 2.2k 2.2k 2.2k SDI SCKI CSBI SDO V− LTC6802-2 IC #1 VREG SDI SCKI CSBI SDO V− CS CK DI DO R12 2.
