Datasheet

LTC6802-1
9
68021fa
PIN FUNCTIONS
GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/Out-
put. The operation of these pins depends on the state of
the MMB pin.
When MMB is high, the pins behave as traditional GPIOs.
By writing a “0” to a GPIO configuration register bit, the
open drain output is activated and the pin is pulled to V
–
.
By writing a logic “1” to the configuration register bit, the
corresponding GPIO pin is high impedance. An external
resistor is needed to pull the pin up to V
REG
.
By reading the configuration register locations GPIO1
and GPIO2, the state of the pins can be determined. For
example, if a “0” is written to register bit GPIO1, a “0” is
always read back because the output NMOSFET pulls pin
38 to V
–
. If a “1” is written to register bit GPIO1, the pin
becomes high impedance. Either a “1” or a “0” is read
back, depending on the voltage present at pin 38. The
GPIOs makes it possible to turn on/off circuitry around
the LTC6802-1, or read logic values from a circuit around
the LTC6802-1.
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See Monitor Mode in the Applications
Information section.
V
MODE
(Pin 40): Voltage Mode Input. When V
MODE
is tied to
V
REG
, the SCKI, SDI, SDO, and CSBI pins are configured as
voltage inputs and outputs. This means these pins accept
standard TTL logic levels. Connect V
MODE
to V
REG
when
the LTC6802-1 is the bottom device in a daisy chain.
When V
MODE
is connected to V
–
, the SCKI, SDI, and CSBI
pins are configured as current inputs and outputs, and SDO
is unused. Connect V
MODE
to V
–
when the LTC6802-1 is
being driven by another LTC6802-1 in a daisy chain.
SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces
to any logic gate (TTL levels) if V
MODE
is tied to V
REG
. SCKI
must be driven by the SCKO pin of another LTC6802-1 if
V
MODE
is tied to V
–
. See Serial Port in the Applications
Information section.
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
any logic gate (TTL levels) if V
MODE
is tied to V
REG
. SDI
must be driven by the SDOI pin of another LTC6802-1 if
V
MODE
is tied to V
–
. See Serial Port in the Applications
Information section.
SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS
open drain output if V
MODE
is tied to V
REG
. SDO is not used
if V
MODE
is tied to V
–
. See Serial Port in the Applications
Information section.
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
pin interfaces to any logic gate (TTL levels) if V
MODE
is tied
to V
REG
. CSBI must be driven by the CSBO pin of another
LTC6802-1 if V
MODE
is tied to V
–
. See Serial Port in the
Applications Information section.