LTC6802-1 Multicell Battery Stack Monitor FEATURES DESCRIPTION n The LTC®6802-1 is a complete battery monitoring IC that includes a 12-bit ADC, a precision voltage reference, a high voltage input multiplexer and a serial interface. Each LTC6802-1 can measure up to 12 series connected battery cells with an input common mode voltage up to 60V. In addition, multiple LTC6802-1 devices can be placed in series to monitor the voltage of each cell in a long battery string.
LTC6802-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW Total Supply Voltage (V+ to V–) .................................60V Input Voltage (Relative to V–) C1 ............................................................ –0.3V to 9V C12 .......................................... V+ – 0.6V to V+ + 0.3V Cn (Note 5) ......................... –0.3V to min (9 • n, 60V) Sn (Note 5) ......................... –0.3V to min (9 • n, 60V) CSBO, SCKO, SDOI .................. V+ – 0.6V to V+ + 0.
LTC6802-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications VACC VERR VCELL VCM VREF Measurement Resolution Quantization of the ADC l ADC Offset Voltage (Note 2) l –0.5 0.5 mV ADC Gain Error (Note 2) l –0.12 –0.22 0.12 0.
LTC6802-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
LTC6802-1 TYPICAL PERFORMANCE CHARACTERISTICS Cell Measurement Total Unadjusted Error vs Input Resistance Cell Measurement Total Unadjusted Error TOTAL UNADJUSTED ERROR (mV) TOTAL UNADJUSTED ERROR (mV) 6 4 2 0 –2 –4 –6 –8 –10 0 25 10 TA = –40°C TA = 25°C TA = 85°C TA = 125°C 8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V) 20 –10 –20 –30 –40 RS = 1k RS = 2k RS = 5k RS = 10k –60 RS IN SERIES WITH CN AND CN-1 –70 NO EXTERNAL CAPACITANCE ON CN AND CN-1 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
LTC6802-1 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage Standby Cell Input Bias Current During Conversion 60 CELL INPUT = 3.6V STANDBY SUPPLY CURRENT (μA) C PIN BIAS CURRENT (μA) 2.65 2.60 2.55 2.50 2.45 2.40 2.35 –40 –20 50 20 40 60 80 TEMPERATURE (°C) 40 TA = –40°C 30 20 TA = 25°C 10 100 120 0 10 20 30 40 SUPPLY VOLTAGE (V) 50 1 0 –1 –2 DEVICE IN STANDBY PRIOR TO MAKING DIE MEASUREMENTS TO MINIMIZE SELF-HEATING –4 –5 –50 0.
LTC6802-1 TYPICAL PERFORMANCE CHARACTERISTICS Internal Discharge Resistance vs Cell Voltage VREG Line Regulation 5.5 50 VREG (V) DISCHARGE RESISTANCE (Ω) TA = 85°C 5.0 TA = –40°C 4.5 TA = 25°C 4.0 3.5 3.0 NO EXTERNAL LOAD ON VREG, CDC = 2 (CONTINUOUS CELL CONVERSIONS) 5 15 TA = –45°C TA = 25°C TA = 85°C TA = 105°C 45 25 35 45 SUPPLY VOLTAGE (V) 40 35 30 25 20 15 10 5 0 55 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
LTC6802-1 PIN FUNCTIONS CSBO (Pin 1): Chip Select Output (Active Low). CSBO is a buffered version of the chip select input, CSBI. CSBO drives the next IC in the daisy chain. See Serial Port in the Applications Information section. SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to and from the next IC in the daisy chain. See Serial Port in the Applications Information section. SCKO (Pin 3): Serial Clock Output. SCKO is a buffered version of SCKI. SCKO drives the next IC in the daisy chain.
LTC6802-1 PIN FUNCTIONS GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/Output. The operation of these pins depends on the state of the MMB pin. When MMB is high, the pins behave as traditional GPIOs. By writing a “0” to a GPIO configuration register bit, the open drain output is activated and the pin is pulled to V–. By writing a logic “1” to the configuration register bit, the corresponding GPIO pin is high impedance. An external resistor is needed to pull the pin up to VREG.
LTC6802-1 BLOCK DIAGRAM 4 V+ 5 REGULATOR C12 VREG 34 10k 6 7 S12 WATCHDOG TIMER WDTB C11 SCKO SDOI 10k CSBO 24 S3 Δ∑ A/D CONVERTER MUX 25 12 RESULTS REGISTER AND COMMUNICATIONS C2 CSBI SDO 10k 26 SDI S2 SCKI 27 C1 REFERENCE VMODE 10k 28 29 GPIO2 CONTROL S1 NC GPIO1 MMB V– 10Ω 30 37 TOS 3 2 1 44 43 42 41 40 39 38 36 35 EXTERNAL TEMP DIE TEMP VTEMP1 31 VTEMP2 32 VREF 33 68021 BD 68021fa 10
LTC6802-1 TIMING DIAGRAM Timing Diagram of the Serial Interface t4 t1 t2 t6 t3 t7 SCKI D3 SDI D2 D1 D7 … D4 D0 D3 t5 CSBI t8 SDO D4 D3 D2 PREVIOUS COMMAND D1 D0 D7 … D4 CURRENT COMMAND D3 68021 TD OPERATION THEORY OF OPERATION The LTC6802-1 is a data acquisition IC capable of measuring the voltage of 12 series connected battery cells. An input multiplexer connects the batteries to a 12-bit delta-sigma analog to digital converter (ADC).
LTC6802-1 OPERATION BATTERY POSITIVE 350V CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 LTC6802-1 IC #8 CSBI SDO SDI SCKI BATTERIES #25 TO #84 AND LTC6802-1 ICs #3 TO #7 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 LTC6802-1 IC #1 V2– OE2 LTC6802-1 IC #2 CSBI SDO SDI SCKI VMODE G
LTC6802-1 OPERATION pulled down by the 100μA current source during the B3 cell measurement AND during the B4 cell measurement. This will tend to decrease the B3 measurement result and increase the B4 measurement result relative to the normal STCVAD command. The biggest change is observed in the B4 measurement when C3 is open. So, the best method to detect an open wire at input C3 is to look for an increase in the measurement of the cell connected between inputs C3 and C4 (cell B4).
LTC6802-1 OPERATION through C11 by looking at the measurements of cells B2 through B12. Therefore the algorithm cannot be used to determine if the topmost C pin is open. Fortunately, an open wire from the battery to the top C pin usually means the V+ pin is also floating. When this happens, the readings for the top battery cell will always be 0V, indicating a failure.
LTC6802-1 OPERATION POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the pins S1 through S12 can be used to discharge battery cells. An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6802-1. Excessive heat results in elevated die temperatures. The electrical characteristics are guaranteed for die temperatures up to 85°C.
LTC6802-1 APPLICATIONS INFORMATION USING THE LTC6802-1 WITH LESS THAN 12 CELLS The LTC6802-1 can typically be used with as few as four cells. The minimum number of cells is governed by the supply voltage requirements of the LTC6802-1. The sum of the cell voltages must be 10V to guarantee that all electrical specifications are met. Figure 5 shows an example of the LTC6802-1 when used to monitor seven cells. The lowest C inputs connect to the seven cells and the upper C inputs connect to V+.
LTC6802-1 APPLICATIONS INFORMATION MODES OF OPERATION The LTC6802-1 has three modes of operation: standby, measure and monitor. Standby mode is a power saving state where all circuits except the serial interface are turned off. In measure mode, the LTC6802-1 is used to measure cell voltages and store the results in memory. Measure mode will also monitor each cell voltage for overvoltage (OV) and undervoltage (UV) conditions. In monitor mode, the device will only monitor cells for UV and OV conditions.
LTC6802-1 APPLICATIONS INFORMATION BATTERY POSITIVE 350V LTC6802-1 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 LTC6802-1 IC #8 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V− S1 C1 S2 C2 S3 C3 IC #3 TO IC #7 LTC6802-1 CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB MMB T
LTC6802-1 APPLICATIONS INFORMATION Table 1. Monitor Mode Cell Selection WDTB GPIO2 GPIO1 CELL INPUTS MONITORED 0 0 0 Cells 1 to 5 0 0 1 Cells 1 to 6 0 1 0 Cells 1 to 7 0 1 1 Cells 1 to 8 1 0 0 Cells 1 to 9 1 0 1 Cells 1 to 10 1 1 0 Cells 1 to 11 1 1 1 Cells 1 to 12 If MMB is low then brought high, all device configuration values are reset to the default states including the VUV, VOV, and CDC configuration bits.
LTC6802-1 APPLICATIONS INFORMATION The voltage mode pin (VMODE) determines whether the low side serial port is configured as voltage mode or current mode. For the bottom device in a daisy-chain stack, this pin must be pulled high (tied to VREG). The other devices in the daisy chain must have this pin pulled low (tied to V–) to designate current mode communication. To designate the top-of-stack device for polling commands, the TOS pin on the top device of a daisy chain must be tied high.
LTC6802-1 APPLICATIONS INFORMATION CSBI SCKI SDI MSB (CMD) BIT6 (CMD) SDO LSB (CMD) POLL STATE 68021 F10 Figure 10. Transmission Format (Poll) Network Layer Broadcast Commands: A broadcast command is one to which all devices on the bus will respond. See the Bus Protocols and Commands sections. In daisy chained configurations, all devices in the chain receive the command bytes simultaneously.
LTC6802-1 APPLICATIONS INFORMATION out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition. Level polling—Daisy-Chained Broadcast Polling: The SDO pin (bottom device) or SDI pin (stacked devices) will be low if a device is busy/in interrupt.
LTC6802-1 APPLICATIONS INFORMATION Commands Table 6.
LTC6802-1 APPLICATIONS INFORMATION Memory Map Table 7 through Table 12 show the memory map for the LTC6802-1. Table 12 gives bit descriptions. Table 7.
LTC6802-1 APPLICATIONS INFORMATION Table 9. Flag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FLGR0 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C10OV C10UV C9OV C9UV * Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high Table 10.
LTC6802-1 APPLICATIONS INFORMATION Table 12.
LTC6802-1 APPLICATIONS INFORMATION SERIAL COMMAND EXAMPLES LTC6802-1 (Daisy Chained Configuration) Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T) Write Configuration Registers 1. 2. 3. 4. 5. 6.
LTC6802-1 APPLICATIONS INFORMATION Poll Interrupt Status (Level Polling) 1. 2. 3. 4. Pull CSBI low Send PLINT command byte SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high Pull CSBI high to exit polling FAULT PROTECTION Overview Care should always be taken when using high energy sources such as batteries. There are numerous ways that systems can be [mis-]configured that might affect a battery system during its useful lifespan.
LTC6802-1 APPLICATIONS INFORMATION Battery Interconnection Integrity The FMEA scenarios that are potentially most damaging are those that involve a break in the stack of battery cells. When the battery stack has a discontinuity between groupings of cells monitored by LTC6802-1 ICs, any load will force a large reverse potential on the daisy-chain connection. This situation might occur in a modular battery system during initial installation or a service procedure.
LTC6802-1 APPLICATIONS INFORMATION Cell-Voltage Filtering The LTC6802-1 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conversion window, provided there isn’t noise aliasing with respect to the delta-sigma modulator rate of 512kHz. This indicates that a lowpass filter with useful attenuation at 500kHz may be beneficial.
LTC6802-1 APPLICATIONS INFORMATION in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since VREF is shutdown during the LTC6802-1 idle and shutdown modes, the thermistor drive is also shut off and thus power dissipation minimized. Since VREG remains always on, the buffer op amp (LT6000 shown) is selected for its ultralow power consumption (10μA).
LTC6802-1 APPLICATIONS INFORMATION stack potential. Figure 18 shows a means of providing both of these features. A resistor divider is used to provide a low-voltage representation of the full stack potential (C12 to C0 voltage) with MOSFETs that decouple the divider current under unneeded conditions. Other MOSFETs, in conjunction with an op amp having a shutdown mode, form a voltage selector that allows measurement of the normal cell1 potential (when GPIO1 is low) or a buffered MUX signal.
LTC6802-1 APPLICATIONS INFORMATION PROVIDING HIGH-SPEED OPTO-ISOLATION OF THE SPI DATA-PORT Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6802-1 require more power on the isolated (battery) side than can be furnished by the VREG output of the LTC6802-1. To keep battery drain minimal, this means that a DC/DC function must be implemented along with a suitable data isolation circuit, such as shown in Figure 19.
LTC6802-1 APPLICATIONS INFORMATION PCB LAYOUT CONSIDERATIONS ADVANTAGES OF DELTA-SIGMA ADCS The VREG and VREF pins should be bypassed with a 1μF capacitor for best performance. The LTC6802-1 employs a delta sigma analog to digital converter for voltage measurement. The architecture of delta sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then filtered or averaged to produce the digital output code.
LTC6802-1 APPLICATIONS INFORMATION Converter Details Each conversion consists of two phases – an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greatly improving CMRR. The second half of the conversion is the actual measurement. Noise Rejection Figure 21 shows the frequency response of the ADC. The rolloff follows a Sinc2 response, with the first notch at 4kHz.
LTC6802-1 PACKAGE DESCRIPTION G Package 44-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1754 Rev Ø) 12.50 – 13.10* (.492 – .516) 1.25 p0.12 7.8 – 8.2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 5.3 – 5.7 0.25 p0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 – 5.60* (.197 – .221) PARTING LINE 0.10 – 0.25 (.004 – .010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2.0 (.079) MAX 1.65 – 1.85 (.065 – .073) 0o – 8o 0.
LTC6802-1 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 01/10 Text Changes to Description Additions to Absolute Maximum Ratings Changes to Electrical Characteristics Changes to Graph G02 Text Changes to Pin Functions Open Connection Detection Section Replaced Text Changes to Operation Section Figures 1, 6 Title Changes Text Changes to Applications Information Section Edits to Tables 6, 7, 12, 13 1 2 3, 4 5 8 11, 13 11, 13, 14 12, 18 16, 28, 29, 30, 31 23, 24, 26, 28 Edit to Figure 12 29 Edit
LTC6802-1 TYPICAL APPLICATION Cascadable 12-Cell Li-Ion Battery Monitor CASCADED SPI PORT TO NEXT LTC6802-1 CSBO SDIO SCKO PRTR5V0U4D RS07J RS07J RS07J CELL12 BLM31PG330SN1L 100Ω CMHZ5265B BAT46W BAT46W BAT46W BAT46W BAT46W 2 5 3 4 LTC6802-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 BAT46W C12FILTER DC12 C11FILTER DC11 C10FILTER DC10 C9FILTER DC9 REPEAT INPUT CIRCUITS FOR CELL3 TO CELL12 100Ω 6 1M 20Ω 100nF 20Ω 1 C8FILTER DC8 C7FILTER DC7 C6FILTER DC6 C5FILTER DC5 C4