Datasheet

LTC6655
16
6655fd
For more information www.linear.com/LTC6655
applicaTions inForMaTion
PC Board Layout
The LTC6655 reference is a precision device that is fac-
tory trimmed to an initial accuracy of ±0.025%, as shown
in the T
ypical Per
formance Characteristic section. The
mechanical stress caused by soldering parts to a printed
circuit board may cause the output voltage to shift and
the temperature coefficient to change.
To reduce the effects of stress-related shifts, mount the
reference near the short edge of a printed circuit board
or in a corner. In addition, slots can be cut into the board
on two sides of the device to reduce mechanical stress.
A thicker and smaller board is stiffer and less prone to
bend. Finally, use stress relief, such as flexible standoffs,
when mounting the board.
Additional precautions include making sure the solder
joints are clean and the board is flux free to avoid leakage
paths. A sample PCB layout is shown in Figure 15.
The V
OUT_S
pin sinks 2mA, which is unusual for a Kelvin
connection. However, this is required to achieve the ex-
ceptional low noise performance. The I • R drop on the
V
OUT_S
line directly affects load regulation. The V
OUT_S
trace should be as short and wide as practical to minimize
series resistance The V
OUT_S
trace adds error as R
TRACE
• 2mA, so a 0.1Ω trace adds 200µV error. The V
OUT_F
pin
is not as important as the V
OUT_S
pin in this regard. An
I • R drop on the V
OUT_F
pin increases the minimum supply
voltage when sourcing current, but does not directly affect
load regulation. For light loading of the output (maximum
output current <100µA), V
OUT_S
should be tied to V
OUT_F
by the shortest possible path to reduce errors caused by
resistance in the sense trace.
Careful attention to grounding is also important, espe
-
cially when sourcing current. The return load current can
produce an
I • R drop causing poor load regulation. Use
a “star” ground connection and minimize the ground to
load metal resistance. Although there are several pins that
are required to be connected to ground, Pin 4 is the actual
ground for return current.
Optimal Noise Performance
The LTC6655 offers extraordinarily low noise for a bandgap
reference—only 0.25ppm in 0.1Hz to 10Hz. As a result,
system noise performance may be dominated by system
design and physical layout.
Some care is required to achieve the best possible noise
performance. The use of dissimilar metals in component
leads and PC board traces creates thermocouples. Varia
-
tions in thermal resistance, caused by uneven air flow,
create differential lead temperatures, thereby causing
thermoelectric
voltage noise at the output of the refer
-
ence. Minimizing the number of thermocouples, as well
as limiting airflow, can substantially reduce these errors.
Additional information can be found in Linear T
echnology
Application Note 82. Position the input and load capacitors
close to the part. Although the LTC6655 has a DC PSRR
of over 100dB, the power supply should be as stable as
possible to guarantee optimal performance. A plot of the
0.1Hz to 10Hz low frequency noise is shown in the Typical
Figure 15. Sample PCB Layout
6655 F14
GND
V
OUT
V
IN
Load Regulation
To take advantage of the V
OUT
Kelvin force/sense pins,
the V
OUT_S
pin should be connected separately from the
V
OUT_F
pin as shown in Figure 16.
LTC6655-2.5
2
7
2mA
LOAD
STAR
MINIMIZE RESISTANCE
OF METAL
6
4
6655 F15
+
Figure 16. Kelvin Connection for Good Load Regulation