Datasheet

LTC6603
23
6603fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
TYPICAL APPLICATIONS
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
LTC6603 Parallel Clock Control
LTC6603 SPI Clock Control
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
6603 TA02
+INA
V+
IN
V+
A
V+
D
–INA
+INB
–INB
CAP
GAIN1
GAIN0(D0)
GND
GND
R
BIAS
V
OCM
+OUTA
–OUTA
+OUTB
–OUTB
CLKCNTL
SDO
SDI
LPF0(SCLK)
LPF1(CS)
CLKIO
SER
LTC6603
0.
1
3V
1216
3V
0.1µF
0.1µF
24
23
20
22
21
25
14
7
8
4
3
19
18
5
11
10
6
9
13
12
15
17
R3 R1
V
OCM
R2
DIODES INC
DMN2004DWK
CLK1
CLK1 CLK0
0 0 R
BIAS1
f
CLK1
0 1 R
BIAS2
f
CLK2
1 0 R
BIAS3
f
CLK3
1 1 R
BIAS4
f
CLK4
R
BIAS1
> R
BIAS2
OR R
BIAS3
R
BIAS
=
R
BIAS
IN k
f
CLK
in MHz
R1 = R
BIAS1
R2 = R3 = R
BIAS4
=
CLK0
LPF1
LPF0
GAIN1
GAIN0
2472
f
CLK
DESIGN PROCEDURE
1. CHOOSE f
CLK1
, f
CLK2
AND f
CLK3
2. CALCULATE R
BIAS1
, R
BIAS2
AND R
BIAS3
3. CALCULATE R2, R3 AND R
BIAS4
R
BIAS1
• R
BIAS2
R
BIAS1
– R
BIAS2
R
BIAS1
• R
BIAS3
R
BIAS1
– R
BIAS3
R1 • R2 • R3
R1 • (R2 + R3) + R2 • R3
6603 TA03
+INA
V+
IN
V+
A
V+
D
–INA
+INB
–INB
CAP
GAIN1
GAIN0(D0)
GND
GND
R
BIAS
V
OCM
+OUTA
–OUTA
+OUTB
–OUTB
CLKCNTL
SDO
SDI
LPF0(SCLK)
LPF1(CS)
CLKIO
SER
LTC6603
0.1µF
3V
1216
3V
0.1µF
0.1µF
24
23
20
22
21
25
14
7
8
4
3
19
18
5
11
10
6
9
13
12
15
17
CS
SCLK
SDI
V
OUT
GND
V+
0.1µF
3V
4
5
6
3
2
1
R1
V
B
V
C
R2
CS1 CS2SCK SDI
LTC2630
8-BIT DAC
IF R1 = 51.1k and R2 = 78.7k THEN
THE f
CLK
RANGE IS 12.36MHz to 80MHz
DAC V
OUT
RANGE 0V TO 2.5V
(USING THE LTC2630 INTERNAL REFERENCE)
R1 =
V
C
RANGE 0V to 2.5V, V
B
= 1.17V
IF V
C
= 0V THEN f
CLK
= f
CLKHI
IF V
C
= 2.5V THEN f
CLK
= f
CLKLO
5.282 • 10
12
1.137f
CLKHI
+ f
CLKLO
, R2 =
5.282 • 10
12
f
CLKHI
– f
CLKLO
f
CLK
= 2.472 • 10
12
R1+ R2
R1• R2

V
C
V
B
•R2






PACKAGE DESCRIPTION