Datasheet
LTC6602
13
6602fc
APPLICATIONS INFORMATION
Theory of Operation (Refer to Block Diagram)
The LTC6602 features two matched filter channels, each
containing gain control, lowpass, and highpass networks
that are controlled by a single control block and clocked by
a single clock generator. The gain, lowpass and highpass
sections can be independently programmed. The two
channels are not independent, i.e. if the gain is set to 24dB,
then both channels have a gain of 24dB. The filter can also
be programmed to bypass the highpass filter networks,
giving a lowpass response. The filter can be clocked with
an external clock source, or using the internal oscillator. A
resistor connected to the R
BIAS
pin sets the bias currents
for the filter networks and the internal oscillator frequency
(unless driven by an external clock). Altering the clock
frequency changes the filter bandwidths. This allows the
filters to be “tuned” to many different bandwidths.
Pin Programmable Interface
As shown in Figure 1, connecting SER to V+
D
allows the
filter to be directly controlled through the pin programmable
control lines GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0.
The HPF0(SDO) and GAIN0(D0) pins are bidirectional (in-
puts in pin programmable control mode, outputs in serial
mode). In pin programmable control mode, the voltages
at HPF0(SDO) and GAIN0(D0) cannot exceed V+
D
; oth-
erwise, large currents can be injected to V+
D
through the
internal diodes (see Figure 2). Connecting a 10k resistor
at the HPF0(SDO) and GAIN0(D0) pins (see Figure 1) is
recommended for current limiting, to less than 10mA. SER
has an internal pull-up to V
+D
. None of the logic inputs
have an internal pull-up or pull-down.
Figure 1. Filter in Pin Programmable Control Mode
V+
IN
V+
A
V+
D
+INA
–INA
SER
LPF1(CS)
LPF0(SCLK)
HPF1(SDI)
HPF0(SDO)
GAIN1
GAIN0(D0)
GND
LTC6602
V
OUT
V
IN
0.1µF
LOWPASS CUTOFF = 900kHz (f
CLK
= 90MHz)
HIGHPASS CUTOFF = 90kHz (f
CLK
= 90MHz)
GAIN = 16
GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.
10k RESISTORS ON HPF0(SDO) AND GAIN0(D0)
PROTECT THE DEVICE IF V
HPF0
> V+
D
OR
V
GAIN0
> V+
D
µP
+
–
+
–
+
–
+
–
10k
10k
6602 F01
+OUTA
–OUTA
V+
IN
V+
A
V+
D
+INA
–INA
SER
LPF1(CS)
LPF0(SCLK)
HPF1(SDI)
HPF0(SDO)
GAIN1
GAIN0(D0)
GND
V
OUT
V
IN
+OUTA
–OUTA
3.3V
0.1µF
3.3V
LTC6602
LPF1
LPF0
HPF1
HPF0
GAIN1
GAIN0