Datasheet

LTC6417
22
6417f
applicaTions inForMaTion
The V
OR
pin, as shown in Figure 9, is internally connected
to a current source sourcing 2mA, plus an internal 20k
resistor pull-down to GND. An internal clamp limits the
maximum output to 3.4V. As soon as one of the inputs
goes beyond the limits, and therefore engages one of the
clamps, the output current, hence, the V
OR
voltage goes
to zero. The dynamic response of the V
OR
pin can be ad-
justed with an external resistor and an optional external
capacitor. For a high speed operation, add a 50Ω resistor
from V
OR
to GND, resulting in a high speed signal with
100mV swing.
The PWRADJ Pin
The voltage applied to the PWRADJ pin scales the supply
current and performance of the LTC6417. This is useful
for reducing power consumption in applications where
linearity of the LTC6417 exceeds the linearity of the other
components in the system; hence LTC6417’s linearity can
be derated without effecting system performance. PWRADJ
is a high impedance input. It has an input impedance of
14.5k. On a 5V supply, PWRADJ self-biases to 1.6V. For full
power, simply connect PWRADJ to the positive supply V
+
.
For minimum power, short the PWRADJ pin to GND. The
PWRADJ pin should be bypassed with a 0.1µF capacitor as
close to the LTC6417 as possible. LTC6417 performance
vs PWRADJ can be found in the graphs.
The SHDN Pin
When pulled high, the SHDN pin puts the LTC6417 in sleep
mode, significantly reducing supply current. SHDN is a high
impedance input. It has an input impedance of 10.5kΩ. If
the SHDN pin is not driven with an external voltage, it floats
down to the same potential as GND, keeping the LTC6417
enabled. The SHDN pin should be bypassed with a 0.1µF
capacitor as close to the LTC6417 as possible.
In sleep mode, the input and output stages are turned off,
but the input and output clamps are kept alive to protect
the part against overvoltage.
The supply current in sleep mode is only 24mA, instead
of the typical 125mA. But should the clamps turn on, the
current drawn from the supply can be as high as 180mA.
If a very large signal arrives at the LTC6417, the voltages
applied to the CLHI and V
CM
pins will determine the maxi-
mum and minimum output swing. Once the input signal
returns to the normal operating range, the LTC6417 returns
to linear operation within 2ns. For DC-coupled operation,
the common mode of the input signals might be different
than the voltage on the V
CM
pin. The minimum swing will
still be set by the voltages applied to the V
CM
and CLHI pins.
CLHI is a high impedance input. It has an input impedance
of 4.8k. On a 5V supply, CLHI self-biases to 2.5V. To limit
the signal swing to a subsequent stage’s power supply,
e.g. an ADC such as the LTC2165, simply connect CLHI
to the positive supply pin of the LTC2165. The CLHI pin
should be bypassed with a 0.1µF capacitor as close to the
LTC6417 as possible.
The V
OR
Pin
The V
OR
, overrange pin signals an overrange condition
when one or both inputs exceed the minimum or maximum
signal swing limits set by the CLHI and V
CM
pins.
The LTC6417 V
OR
pin can be used by a control system to
limit the input power dynamically. This is very useful in
applications where the overload response of the complete
system would be too slow.
Figure 9. LTC6417 Internal Topology Showing
V
OR
Pin with Pull-Down Resistor and Clamp
6417 F09
V
OR
20k
I
CL
2mA
LTC6417
GND
V
+