Datasheet

LTC6417
21
6417f
applicaTions inForMaTion
Output Common Mode Adjustment
For AC-coupled applications, the output common mode
voltage is set by the V
CM
pin. An internal buffer, as shown
in Figure 6, couples the voltage on the V
CM
pin to the
inputs via high impedance resistors. Because the input
common mode voltage is approximately the same as the
output common mode voltage, both are approximately
equal to the voltage applied to the V
CM
pin. For DC-coupled
applications, the internal V
CM
is overdriven by the input
signal. The V
CM
pin has a Thevenin equivalent resistance
of 2.7k and can be overdriven by an external voltage. The
V
CM
pin floats to a default voltage of 1.25V on a 5V supply.
The output common mode voltage is capable of tracking
V
CM
in a range from 0.29V to 2.25V on a 5.0V supply. The
V
CM
pin can be floated, but it should always be bypassed
close to the LTC6417 with a 0.1µF bypass capacitor to
GND. When interfacing with A/D converters such as the
LTC22xx families, the V
CM
pin can be connected to the
V
CM
output pin of the ADC, as shown in Figure 5.
Clamping, the CLHI Pin and the V
CM
Pin
The CLHI pin is used to set the high side clamp voltage
of the high speed internal circuitry.
This limits the single-ended maximum and minimum
voltage excursion at each of the outputs. This feature is
extremely important in applications with input signals
having very large peak-to-average ratios such as cellular
base station receivers.
Internal circuitry generates a symmetric low side clamp
voltage with respect to the common mode voltage V
CM
(Figures 7 and 8). The LTC6417 clamp control circuitry
features two additional mechanisms. First, internally im-
posed maximum swing of 2.5V and minimum swing of 0.2V
ensure that the transistors do not go into deep saturation.
This ensures a quick recovery after the clamps are released.
Second, if CLHI voltage is less than V
CM
, internal CLLO
starts to track CLHI. This limits output swing and protects
output transistors. Since the clamp response is on the
order of 5ns to clamp and 1ns to release, clamp circuit
becomes less effective at frequencies beyond 160MHz.
Figure 6. LTC6417 Internal Topology Showing
the Common Mode Buffer Biasing the Inputs
6417 F06
x1
x1
1.5Ω
10.8k
V
+
IN+
OUT+
OUT–IN–
GND
V
CM
3.6k
9.25k
9.25k
x1
1.5Ω
LTC6417
Figure 7. Internal Circuitry Generating Symmetric
Clamp Voltages with Respect to V
CM
Figure 8. Symmetric High- and Low-Side Clamp
Voltages with Respect to V
CM
6417 F07
x1
–
+
V
+
CLHI
CLHI (INT)
CLLO (INT)
GND
x2
V
CM
9.6k
9.6k
LTC6417
6417 F08
V
CM
CLHI
CLLO