Datasheet

LTC6417
16
6417f
pin FuncTions
V
+
(Pins 1, 6, 11, 16): Positive Power Supply. Typically 5V.
Split supplies are possible as long as the voltage between
V
+
and GND is 4.75V to 5.25V. Bypass capacitors of 680pF
and 0.1µF as close to the part as possible should be used
between the supplies.
CLHI (Pin 2): High Side Clamp Voltage. The voltage ap-
plied to the CLHI pin defines the upper voltage limit of
the OUT
+
and OUT
–
pins. This voltage should be set at
least 300mV above the upper voltage range of the ADC.
On a 5V supply, the CLHI pin will float to a 2.5V default
voltage. CLHI has a Thevenin equivalent of approximately
4.8kΩ and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high quality ceramic
bypass capacitor of at least 0.01µF.
GND (Pins 3, 7, 10, 17, 20, Exposed Pad Pin 21): Nega-
tive Power Supply. Normally tied to ground. All pins and
the exposed pad must be tied to the same voltage. GND
may be tied to a voltage other than ground as long as the
voltage between V
+
and GND is 4.75V to 5.25V. If the GND
pins are not tied to ground, bypass each with 680pF and
0.1µF capacitors as close to the package as possible. The
exposed pad must be soldered to the printed circuit board
ground plane for good heat transfer.
NC (Pins 4, 13): No Connection. These pins are not con-
nected internally.
PWRADJ (Pin 5): Power Adjust Voltage. The voltage
applied to this pin scales the bias current internal to the
LTC6417. The PWRADJ pin will float to a 1.6V default
voltage. PWRADJ has a Thevenin equivalent resistance of
approximately 14.5k and can be overdriven by an external
voltage. The PWRADJ pin should be bypassed with a high
quality ceramic bypass capacitor of at least 0.01µF.
IN
+
, IN
–
(Pin 8, Pin 9): Non-inverting and inverting input
pins of the buffer, respectively. These pins are high imped-
ance, approximately 9.5k. If AC-coupled, these pins will
self bias to the voltage applied to the V
CM
pin.
SHDN (Pin 12): This pin puts the LTC6417 in sleep mode
when pulled high. If no voltage is applied to the SHDN pin,
it floats down to the same potential as GND.
V
OR
(Pin 14): Overrange Output. This pin, by default at
3.4V, will be pulled down to GND, when one or both input
signals go beyond the minimum or maximum swing set
by the CLHI and V
CM
pins.
V
CM
(Pin 15): This pin sets the output common mode volt-
age seen at OUT
+
and OUT
–
by driving IN
+
and IN
–
through
a buffer with a high output resistance of 9.5k. The V
CM
pin has a Thevenin equivalent resistance of approximately
2.7k and can be overdriven by an external voltage. If no
voltage is applied to V
CM
, it will float to a default voltage of
approximately 1.25V on a 5V supply. The V
CM
pin should
be bypassed with a high quality ceramic bypass capacitor
of at least 0.01µF.
OUT
–
, OUT
+
(Pin 18, Pin 19): Outputs.