Datasheet

LTC6412
3
6412fa
DC ELECTRICAL CHARACTERISTICS
The l denotes specifi cations that apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. DC electrical performance measured using DC test circuit schematic.
V
IN(DIFF)
is defi ned as (+IN) – (–IN). V
OUT(DIFF)
is defi ned as (+OUT) – (–OUT). V
IN(CM)
is defi ned as [(+IN) + (–IN)]/2. V
OUT(CM)
is
defi ned as [(+OUT) + (–OUT)]/2. Unless noted otherwise, default operating conditions are V
CC
= 3.3V, EN = 0.8V, SHDN = 2.2V, +V
G
tied
to V
REF
(negative gain slope mode), V
OUT(CM)
= 3.3V. Differential power gain defi ned at Z
SOURCE
= 50Ω differential and Z
LOAD
= 200Ω
differential.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gain Characteristics
G
MAX
Maximum Differential Power Gain (Note 4) –V
G
= 0V, V
IN(DIFF)
= 100mV
l
16.1
15.5
17.1 18.1
18.7
dB
dB
G
MIN
Minimum Differential Power Gain (Note 4) –V
G
= 1.2V, V
IN(DIFF)
= 200mV
l
–16.2
–16.8
–14.9 –13.6
–13.0
dB
dB
G
RANGE
Differential Power Gain Range G
MAX
-G
MIN
l
30.7
30.1
31.9 33.1
33.7
dB
dB
TC
GAIN
Temperature Coeffi cient of Gain at Fixed V
G
–V
G
= 0V to 1.2V –0.007 dB/°C
G
SLOPE
Gain Control Slope –V
G
= 0.2V to 1.0V, 85 Points, Slope of the
Least-Square Fit Line
l
–34.1
–34.7
–32.9 –31.7
–31.1
dB/V
dB/V
G
CONF(AVE)
Average Conformance Error to Gain Slope Line –V
G
= 0.2V to 1.0V, 85 Points, Standard
Error to the Least-Square Fit Line
0.12 0.20 dB
G
CONF(MAX)
Maximum Conformance Error to Gain Slope
Line
–V
G
= 0.2V to 1.0V, 85 points, Maximum
Error to the Least-Square Fit Line
0.20 0.45 dB
+IN and –IN Pins
R
IN(GMAX)
Differential Input Resistance at Maximum Gain –V
G
= 0V, V
IN(DIFF)
= 100mV
l
49
47
57 65
67
Ω
Ω
R
IN(GMIN)
Differential Input Resistance at Minimum Gain –V
G
= 1.2V, V
IN(DIFF)
= 200mV
l
49
47
57 65
67
Ω
Ω
V
INCM(GMAX)
Input Common Mode Voltage at Maximum Gain –V
G
= 0V, DC Blocking Capacitor to Input 640 mV
V
INCM(GMIN)
Input Common Mode Voltage at Minimum Gain –V
G
= 1.2V, DC Blocking Capacitor to Input 640 mV
+V
G
, –V
G
, and V
REF
Pins
R
IH(+VG)
+V
G
Input High Resistance +V
G
= 1.0V, –V
G
Tied to V
REF
,
R
IN(+VG)
= 1V/Δ I
IL(+VG)
l
7.8
7.2
9.2 10.6
11.6
kΩ
kΩ
R
IH(–VG)
–V
G
Input High Resistance –V
G
= 1.0V, +V
G
Tied to V
REF
,
R
IN(–VG)
= 1V/Δ I
IL(–VG)
l
7.8
7.2
9.2 10.6
11.6
kΩ
kΩ
I
IL(+VG)
+V
G
Input Low Current +V
G
= 0V, –V
G
Tied to V
REF
l
–9
–10
–5 –1
–1
μA
μA
I
IL(–VG)
–V
G
Input Low Current –V
G
= 0V, +V
G
Tied to V
REF
l
–9
–10
–5 –1
–1
μA
μA
V
REF
Internal Bias Voltage –V
G
= 0V, +V
G
Tied to V
REF
l
590
580
615 640
650
mV
mV