Datasheet

LTC6405
11
6405fb
For more information www.linear.com/6405
pin Functions
V
OCM
(Pin 2/Pin 4): Output Common Mode Reference
Voltage. The voltage on V
OCM
sets the output common
mode voltage level (which is defined as the average of the
voltages on the +OUT and –OUT pins). The V
OCM
voltage
is internally set by a resistive divider between the supplies,
developing a default voltage potential of 2.5V with a 5V
supply. The V
OCM
pin can be over-driven by an external
voltage capable of driving the 19kΩ Thevenin equivalent
impedance presented by the pin. The V
OCM
pin should be
bypassed with a high quality ceramic bypass capacitor of at
least 0.01µF, to minimize common mode noise from being
converted to differential noise by impedance mismatches
both externally and internally to the IC.
V
+
(Pin 3/Pins 2, 10, 11):
V
–
(Pin 6/Pins 3, 9, 12):
Power Supply Pins. It is critical that close attention be
paid to supply bypassing. For single supply applications,
it is recommended that a high quality 0.1µF surface mount
ceramic bypass capacitor be placed between V
+
and V
–
with
direct short connections. In addition, V
–
should be tied
directly to a low impedance ground plane with minimal
routing. For dual (split) power supplies, it is recommended
that
additional high quality, 0.1µF ceramic capacitors are
used to bypass V
+
to ground and V
–
to ground, again
with minimal routing. For driving large loads (<200Ω),
additional bypass capacitance may be needed for optimal
performance. Keep in mind that small geometry (e.g., 0603
or smaller) surface mount ceramic capacitors have a much
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
+OUT, –OUT (Pins 4, 5/Pins 7, 14): Unfiltered Output
Pins. Besides driving the feedback network, each pin
can drive an additional 50Ω to ground with typical short
circuit current limiting of ±60mA. Each amplifier output
is designed to drive a load capacitance of 5pF. Larger
capacitive loads should be decoupled with at least 15Ω
resistors from each output.
V
TIP
(Pin 5) QFN Only: This pin can normally be left float-
ing. It determines which pair of input transistors (NPN or
PNP or both) is sensing the input signal. The V
TIP
pin is
set by an internal resistive divider between the supplies,
developing a default 2.8V voltage with a 5V supply. V
TIP
has a Thevenin equivalent resistance of approximately
17k and can be over-driven by an external voltage. The
V
TIP
pin should be bypassed with a high quality ceramic
bypass capacitor of at least 0.01µF. See the Applications
Information section for more details.
SHDN (Pin 7/Pin 1): When SHDN is floating or directly
tied to V
+
, the LTC6405 is in the normal (active) operating
mode. When the SHDN pin is connected to V
–
, the LTC6405
enters into a low power shutdown state with Hi-Z outputs.
+IN, –IN (Pins 8, 1/Pins 15, 6): Noninverting and Inverting
Input Pins of the Amplifier, Respectively. For best perfor-
mance, it is highly recommended that stray capacitance
be kept to an absolute minimum by keeping printed circuit
connections as short as possible.
+OUTF, –OUTF (Pins 8, 13) QFN Only: Filtered Output
Pins. These pins have a series RC network (R = 50Ω,
C = 3.75pF) connected between the filtered and unfiltered
outputs. See the Applications Information section for
more details.
NC (Pin 16) QFN Only: No Connection. This pin is not
connected internally.
Exposed Pad (Pin 9/Pin 17): Tie the bottom pad to V
–
.
If split supplies are used, DO NOT tie the pad to ground.
(MSOP/QFN)