Datasheet

LTC6404
21
6404f
APPLICATIONS INFORMATION
V
INCM
is defi ned as the average of the two input voltages
V
INP
, and V
INM
(also called the source-referred input com-
mon mode voltage):
VVV
INCM INP INM
=+
()
1
2
•
and V
INDIFF
is defi ned as the difference of the input
voltages:
V
INDIFF
= V
INP
– V
INM
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Setting the differential input to zero (V
INDIFF
= 0), the de-
gree of common mode to differential conversion is given
by the equation:
VVV
VV
V
OUTDIFF OUT OUT
INCM OCM
AVG
I
=
≈
()
Δ
+
–
–•
–
β
β
⏐
NNDIFF
=0
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of both
signals and noise. Using 1% resistors or better will mitigate
most problems, and will provide about 34dB worst-case of
common mode rejection. Using 0.1% resistors will provide
about 54dB of common mode rejection. A low impedance
ground plane should be used as a reference for both the
input signal source, and the V
OCM
pin. A direct short of
V
OCM
to this ground or bypassing the V
OCM
with a high
quality 0.1µF ceramic capacitor to this ground plane, will
further prevent common mode signals from being con-
verted to differential.
There may be concern on how feedback ratio mismatch
affects distortion. Distortion caused by feedback ratio mis-
match using 1% resistors or better is negligible. However,
in single supply level shifting applications where there is
a voltage difference between the input common mode
voltage and the output common mode voltage, resistor
mismatch can make the apparent voltage offset of the
amplifi er appear higher than specifi ed.
The apparent input referred offset induced by feedback
ratio mismatch is derived from the following equation:
V
OSDIFF(APPARENT)
≈ (V
ICM
– V
OCM
) • Δβ
Using the LTC6404-1 in a single supply application on a
single 5V supply with 1% resistors, and the input common
mode grounded, with the V
OCM
pin biased at mid-supply,
the worst-case DC offset can induce 25mV of apparent
offset voltage. With 0.1% resistors, the worst case appar-
ent offset reduces to 2.5mV.
Input Impedance and Loading Effects
The input impedance looking into the V
INP
or V
INM
input
of Figure 1 depends on whether the sources V
INP
and
V
INM
are fully differential. For balanced input sources
(V
INP
= –V
INM
), the input impedance seen at either input
is simply:
R
INP
= R
INM
= R
I
For single ended inputs, because of the signal imbalance
at the input, the input impedance increases over the bal-
anced differential case. The input impedance looking into
either input is:
RR
R
R
RR
INP INM
I
F
IF
==
+
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
1
1
2
–•
Input signal sources with non-zero output impedances can
also cause feedback imbalance between the pair of feedback
networks. For the best performance, it is recommended
that the source’s output impedance be compensated for.
If input impedance matching is required by the source,
R1 should be chosen (see Figure 4):
R
RR
RR
INM S
INM S
1
=
•
–
Figure 4. Optimal Compensation for Signal Source Impedance
V
S
+
–
–
+
R
F
R
F
R
I
R
INM
R
S
R
I
R2 = R
S
|| R1
R1 CHOSEN SO THAT R1 || R
INM
= R
S
R2 CHOSEN TO BALANCE R1 || R
S
R1
6404 F04