Datasheet

LTC6104
11
6104f
APPLICATIONS INFORMATION
If the maximum output current, I
OUT
, is limited to 1mA,
R
OUT
equals 3V/1mA = 3k and R
IN
= 3k/6 – 0.3Ω (internal
device resistance) = 499.7Ω.
The output error due to DC offset is ±510µV (typ) and
the error due to offset current, I
OS
, is 3k • 100nA =
300µV(typ).
The maximum output error can therefore reach ±810µV
or 0.027% (–71dB) of the output full scale. Considering
the system input 60dB dynamic range (I
SENSE
= ±1mA to
±1A), the 71dB performance of the LTC6104 makes this
application feasible.
Output Error, E
OUT
, Due to the Current Mirror Errors,
I
OUT-GAINERR
and I
OUT-OSERR
When V
SENSE
is negative, amplifi er B would be on and
amplifi er A off. The output of amplifi er B drives an internal
current mirror which is connected to the OUT pin. This
current mirror has some error associated with it, and this
error can be calculated as follows:
I
OUT-GAINERR
= ±0.2% • I
OUT
, with I
OUT
= ±1mA,
I
OUT-GAINERR(MAX)
= ±2μA
I
OUT-OSERR
= ±0.2μA
I
OUT-ERR(MAX)
= I
OUT-GAINERR
+ I
OUT-OSERR
= ±2μA +
±0.2μA = ±2.2μA
E
OUT-ERR(MAX)
= I
OUT-ERR(MAX)
• R
OUT
The combined effect of amplifi er offset and current mirror
errors is shown graphically in Figure 4.
Output Error, E
OUT
, Due to Trace Resistance
The LTC6104 uses the +INB pin for both the positive “B”
amplifi er input and the positive supply input for both
amplifi ers. If trace resistance (R
T
) become signifi cant
(Figure 5), this supply current can cause an input offset
error, which can be calculated as follows:
ERI
R
R
OUT OFFSET T S
OUT
IN
()
••=
Trace resistances to the –IN terminals will increase the
effective R
IN
value, causing a gain error (Figure 5). In ad-
dition, internal device resistance will add approximately
0.3Ω to R
IN
.
Gain error equals:
A
R
RR
R
R
V ERROR
OUT
IN T
OUT
IN
()
.
–=
++03Ω
Minimizing resistance in the input traces is important and
care should be taken in the PCB layout. Make the trace
short and wide. Kelvin connection to the shunt resistor
pad should be used. Avoid tapping into this signal along
Figure 5. Errors from PCB Traces and Other Parasitic Resistances
V
SENSE
(mV)
0.1
OUTPUT ERROR (%)
1
10
100
–500 –100 100 300
0.01
–300
500
6104 F04
MAXIMUM
TYPICAL
R
IN
= 100Ω
R
OUT
= 5k
Figure 4. Output Error vs Input Voltage
+
–
8 7 6
4
+INA
OUT
+
–
V
S
I
S
V
S
A
LTC6104
–INA –INB
R
IN
R
IN
R
T
R
T
R
T
TO
CHARGER/LOAD
R
SENSE
V
SENSE
+–
+INB
V
–
I
LOAD
+
CURRENT
MIRROR
+
–
5
B
R
OUT
I
OUT
V
REF
6104 F05
V
OUT
+
–
1
R
T