Datasheet

LTC6090
13
6090fa
applicaTions inForMaTion
Power Dissipation
With a supply voltage of 140V it doesn’t take much current
to consume a lot of power. Consider that 10mA at 140V
consumes 1.4W of power and needs to be dissipated in a
small plastic SO package. To aid in power dissipation both
LTC6090 packages have exposed pads for low thermal
resistance. The amount of metal connected to the exposed
pad will lower the θ
JA
of a package. An optimal amount
of PCB metal connected to the SO package will lower the
junction to ambient thermal resistance down to 33°C/W.
If minimal metal is used, the θ
JA
could more than double
(see Table 1). If the exposed pad has no metal beneath it,
θ
JA
could be as high 120°C/W.
It’s recommended that the exposed pad have as much PCB
metal connected to it as reasonably available. The more PCB
metal connected to the exposed pad, the lower the thermal
resistance. Use multiple vias from the exposed pad to the
V
–
supply plane. The exposed pad is electrically connected
to the V
–
pin. In addition, a heat sink may be necessary
if operating near maximum junction temperature. See
Table 1 for guidance
on how thermal resistance changes
as
a function of metal area connected to the exposed pad.
The LTC6090 is specified to source and sink 10mA at 140V.
If the total supply voltage is dropped across the device,
1.4W of power will need to be dissipated. If the quiescent
power is included (140V • 2.8mA = 0.4W), the total power
dissipated is 1.8W. The internal die temperature will rise
59° using an optimal layout in a SO package. A sub-optimal
layout could more than double the amount of temperature
increase due to power dissipation.
TOP LAYER A TOP LAYER B TOP LAYER C TOP LAYER D
EXAMPLE A EXAMPLE B EXAMPLE C EXAMPLE D
BOTTOM LAYER A
θ
JA
= 43°C/W
θ
JC
= 5°C/W
θ
CA
= 38°C/W
θ
JA
= 50°C/W
θ
JC
= 5°C/W
θ
CA
= 45°C/W
θ
JA
= 57°C/W
θ
JC
= 5°C/W
θ
CA
= 52°C/W
θ
JA
= 54°C/W
θ
JC
= 5°C/W
θ
CA
= 49°C/W
θ
JA
= 57°C/W
θ
JC
= 5°C/W
θ
CA
= 52°C/W
θ
JA
= 58°C/W
θ
JC
= 5°C/W
θ
CA
= 53°C/W
θ
JA
= 72°C/W
θ
JC
= 5°C/W
θ
CA
= 67°C/W
BOTTOM LAYER B BOTTOM LAYER C
MINIMUM BOTTOM LAYER A MINIMUM BOTTOM LAYER B MINIMUM BOTTOM LAYER C
BOTTOM LAYER D
Table 1. Thermal Resistance as PCB Area of Exposed Pad Varies