Datasheet

8
LTC485
sn485 LTC485ffs
APPLICATIO S I FOR ATIO
UU W U
The LTC485 output stage will maintain a high impedance
state until the breakdown of the N-channel or P-channel is
reached when going positive or negative respectively. The
output will be clamped to either V
CC
or ground by a Zener
voltage plus a Schottky diode drop, but this voltage is way
beyond the RS485 operating range. This clamp protects
the MOS gates from ESD voltages well over 2000V.
Because the ESD injected current in the N-well or substrate
consists of majority carriers, latchup is prevented by
careful layout techniques.
Propagation Delay
Many digital encoding schemes are dependent upon the
difference in the propagation delay times of the driver and
the receiver. Using the test circuit of Figure 13, Figures 11
and 12 show the typical LTC485 receiver propagation
delay.
The receiver delay times are:
⏐t
PLH
– t
PHL
⏐ = 9ns Typ, V
CC
= 5V
The driver skew times are:
Skew = 5ns Typ, V
CC
= 5V
10ns Max, V
CC
= 5V, T
A
= –40°C to 85°C
Figure 11. Receiver t
PHL
Figure 12. Receiver t
PLH
D
R
RECEIVER
OUT
R
100Ω
100pF
100pF
TTL IN
t
r
, t
f
< 6ns
BR
LTC485 • F13
Figure 13. Receiver Propagation Delay Test Circuit
LTC485 • F11
RO
B
A
DRIVER
OUTPUTS
RECEIVER
OUTPUT
A
B
RO
RECEIVER
OUTPUT
DRIVER
OUTPUTS
LTC485 • F12