Datasheet

LTC4449
7
4449fa
OPERATION
TIMING DIAGRAM
Figure 1. Three-State Input Operation
V
IL(BG)
V
IL(TG)
V
IL(BG)
90%
IN
TG
BG
90%
10%
t
r(TG)
t
pLH(TG)
10%
t
r(BG)
4449 TD
t
f(BG)
t
f(TG)
t
pLH(BG)
t
pHL(BG)
t
pHL(TG)
Overview
The LTC4449 receives a ground-referenced, low voltage
digital input signal to drive two N-channel power MOSFETs
in a synchronous power supply confi guration. The gate
of the low side MOSFET is driven either to V
CC
or GND,
depending on the state of the input. Similarly, the gate of
the high side MOSFET is driven to either BOOST or TS by
a supply bootstrapped off of the switch node (TS).
Input Stage
The LTC4449 employs a unique three-state input stage with
transition thresholds that are proportional to the V
LOGIC
supply. The V
LOGIC
supply can be tied to the controller
IC’s power supply so that the input thresholds will match
those of the controller’s output signal. Alternatively, V
LOGIC
can be tied to V
CC
to simplify routing. An internal voltage
regulator in the LTC4449 limits the input threshold values
for V
LOGIC
supply voltages greater than 5V.
The relationship between the transition thresholds and
the three input states of the LTC4449 is illustrated in
Figure 1. When the voltage on IN is greater than the
threshold V
IH(TG)
, TG is pulled up to BOOST, turning the
high side MOSFET on. This MOSFET will stay on until IN
falls below V
IL(TG)
. Similarly, when IN is less than V
IH(BG)
,
BG is pulled up to V
CC
, turning the low side (synchronous)
MOSFET on. BG will stay high until IN increases above
the threshold V
IL(BG)
.
The thresholds are positioned to allow for a region in which
both BG and TG are low. An internal resistive divider will
pull IN into this region if the signal driving the IN pin goes
into a high impedance state.
One application of this three-state input is to keep both of
the power MOSFETs off while an undervoltage condition
exists on the controller IC power supply. This can be
accomplished by driving the IN pin with a logic buffer
that has an enable pin. With the enable pin of the buffer
tied to the power good pin of the controller IC, the logic
buffer output will remain in a high impedance state until the
controller confi rms that its supply is not in an undervoltage
state. The three-state input of the LTC4449 will therefore
pull IN into the region where TG and BG are low until the
controller has enough voltage to operate predictably.
TG HIGH
TG HIGH
V
IH(TG)
V
IL(BG)
V
IL(TG)
V
IH(BG)
IN
TG LOW
TG LOW
BG LOW
BG HIGH
4449 F01
BG LOW
BG HIGH