Datasheet

6
LTC4440
4440f
TI I G DIAGRA
UWW
V
IH
90%
10%
t
r
INPUT (INP)
OUTPUT (TG)
INPUT RISE/FALL TIME <10ns
V
IL
t
f
t
PLH
4440 TD
t
PHL
BLOCK DIAGRA
W
BOOST
TS
GND
TG
BOOST
4440 BD
V
IN
UP TO 80V,
TRANSIENT
UP TO 100V
TS
HIGH SIDE
UNDERVOLTAGE
LOCKOUT
UNDERVOLTAGE
LOCKOUT
LEVEL SHIFTER
V
CC
8V TO 15V
GND
INP
Exposed Pad MS8E Package
INP (Pin 1): Input Signal. TTL/CMOS compatible input
referenced to GND (Pin 2).
GND (Pins 2, 4): Chip Ground.
V
CC
(Pin 3): Chip Supply. This pin powers the internal low
side circuitry. A low ESR ceramic bypass capacitor should
be tied between this pin and the GND pin (Pin 2).
NC (Pin 5): No Connect. No connection required. For
convenience, this pin may be tied to Pin 6 (BOOST) on the
application board.
BOOST (Pin 6): High Side Bootstrapped Supply. An exter-
nal capacitor should be tied between this pin and TS
(Pin 8). Normally, a bootstrap diode is connected between
V
CC
(Pin 3) and this pin. Voltage swing at this pin is from
V
CC
– V
D
to V
IN
+ V
CC
– V
D
, where V
D
is the forward voltage
drop of the bootstrap diode.
TG (Pin 7): High Current Gate Driver Output (Top Gate).
This pin swings between TS and BOOST.
TS (Pin 8): Top (High Side) Source Connection.
Exposed Pad (Pin 9): Ground. Must be electrically con-
nected to Pins 2 and 4 and soldered to PCB ground for
optimum thermal performance.
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PI FU CTIO S
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