Datasheet

LTC4425
4
4425f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the maximum specifi ed pin current rating may result in device
degradation or failure.
Note 3: Failure to solder the exposed backside of the package to the PC
board ground plane will result in a thermal resistance much greater than
43°C/W on the DD package and greater than 35°C/W on MSE package.
Note 4: The LTC4425E (E grade) is guaranteed to meet specifi cations
from 0°C to 85°C junction temperature. Specifi cations over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC4425I (I grade) is guaranteed over the full –40°C to 125°C operating
junction temperature range. The junction temperature, T
J
, is calculated
from the ambient temperature, T
A
, and power dissipation, P
D
, according to
the formula:
T
J
= T
A
+ (P
D
• θ
JA
°C/W).
Note that the maximum ambient temperature is determined by specifi c
operating conditions in conjunction with board layout, the rated thermal
package thermal resistance and other environmental factors.
Note 5: V
IN
to V
OUT
charge current is reduced by thermal foldback as
junction temperature approaches 105°C.
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at T
A
= 25°C, V
IN
= 3.8V. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Leakage Balancer
V
MID
V
MID
Output Voltage V
OUT
= 3.6V 1.76 1.8 1.84 V
V
MID
Maximum Current Sourcing Capability V
MID
< V
OUT/2
, V
MID
< V
CLAMP
0.7 mA
V
MID
Maximum Current Sinking Capability V
MID
> V
OUT/2
, V
MID
< V
CLAMP
1.2 mA
PFO, PFI_RET, PFI
Output Low Voltage (PFO, PFI_RET) I
PIN
= 5mA 65 mV
Pin Leakage Current (PFO, PFI_RET) V
PIN
= 5V, EN = 0 1 µA
FB Threshold Voltage for Power Good (Rising) LDO Mode
l
1.09 1.11 1.13 V
Input-to-Output Differential for Power Good (Rising) Normal Mode 265 mV
V
PFI
PFI Threshold (Falling)
l
1.18 1.2 1.22 V
PFI Hysteresis 10 mV
I
PFI
PFI Pin Input Leakage 100 nA
Power Good Timer Delay 200 ms
Logic Inputs (EN, SEL)
V
IL
Logic Low Input Voltage
l
0.4 V
V
IH
Logic High Input Voltage
l
1.2 V
I
IH
Input Current High EN, SEL Pins at 5.5V –1 1 µA
I
IL
Input Current Low EN, SEL Pins at GND –1 1 µA