Datasheet
LTC4425
7
4425fa
For more information www.linear.com/LTC4425
pin FuncTions
V
OUT
(Pin 1, 2): Output Pin of the Charger. Typically con-
nects to the top of the 2-cell supercap stack.
PROG (Pin 3): Charge Current Program and Charge Cur-
rent Monitor Pin. A resistor connected from PROG to
ground programs the charge current. In LDO mode, this
pin always ser
vos to 1V. However, if the charge current
profile is turned on, this pin servos to a voltage between
1V and 0.1V depending on the input-to-output differential.
In all cases, the voltage on this pin always represents the
actual charge current.
SEL (Pin 4): Logic Input to Select One of the Two Pos
-
sible Clamp Voltages (V
CLAMP
). If the pin is a logic low,
the maximum voltage across any supercap of the stack
is 2.45V. If the pin is a logic high, it is 2.7V. Do not float
this pin.
FB (Pin 5): In LDO mode, output voltage is programmed
by a resistor divider from V
OUT
via the FB pin. In this
mode, the voltage on this pin always servos to the internal
reference voltage of 1.2V. If the FB pin is pulled up to V
IN
,
the LDO mode is disabled and the charge current profile
mode is turned on. Shorting the FB pin to GND turns off
charge current profile mode. Do not float this pin.
EN (Pin 6): Digital Input to Enable the Charger. If this pin
is a logic high, the part is enabled and it draws only 20μA
of quiescent current from the input or output when idle.
If this pin is a logic low, the part is in shutdown mode and
draws less than 3μA. Do not float this pin.
PFI_RET (Pin 7): This pin connects to the bottom of the
external resistor divider for the input power-fail compara
-
tor. In shutdown mode, an internal switch opens up this
path to reduce the current drawn by the resistor divider
.
PFO
(Pin 8): Open Drain Output of the Power-Fail Com-
parator. This pin is driven to logic low if at least one of the
following conditions is true: (1) V
IN
is less than a value
programmed by an external divider via PFI, (2) V
OUT
has
not reached within 7.5% of its final programmed value
in LDO mode, or (3) V
OUT
is not within 250mV of V
IN
in
charge current profile mode. When all these conditions
are false for at least 200ms, this pin goes high impedance
indicating that power is good.
PFI (Pin 9): Input to the Power-Fail Comparator. The
input voltage below which PFO pin indicates a power-fail
condition can be programmed by connecting this pin to
an external resistor divider between V
IN
and PFI_RET pin.
V
MID
(Pin 10): Connects to the Midpoint of the 2-Cell
supercap stack. An internal leakage balancing amplifier
drives this pin to a voltage which is exactly half of V
OUT
.
V
IN
(Pin 11, 12): Input Power Pin. Typically connected to a
DC source like a Li-Ion/Polymer battery or a USB port. This
pin should be bypassed with a low ESR ceramic capacitor.
GND (Exposed Pad Pin 13): GND. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
under the part to achieve optimum thermal conduction.
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