Datasheet

LTC4365
17
4365fa
For more information www.linear.com/LTC4365
applicaTions inForMaTion
Note that during initial start-up, the LTC4365-1 will not
turn on the external MOSFETs until a battery is first con-
nected to the V
IN
pin. To begin operation, V
IN
must initially
rise above the 2.2V UVLO lockout voltage. Connecting the
battery ensures that the LTC4365-1 comes out of UVLO.
12V Application with 150V Transient Protection
Figure 20 shows a 12V application that withstands input
supply transients up to 150V. When the input voltage ex
-
ceeds 17.9V, the
OV resistive divider turns off the external
MOSFETs. As V
IN
rises to 150V, the gate of transistor M1
remains in the Off condition, thus preventing conduction
from V
IN
to V
OUT
. Note that M1 must have an operating
range above 150V.
Resistor R6 and diode D3 clamp the LTC4365 supply volt
-
age to 50V. To prevent R6 from interfering with reverse
operation, the recommended value is 1k or less. Note that
the power handling capability of R6 must be considered in
order to avoid overheating during transients. D3 is shown
as a bidirectional clamp in order to achieve reverse-polarity
protection at V
IN
. M2 is also required in order to protect
V
OUT
from negative voltages at V
IN
and should have an
operating range beyond the breakdown of D3. If reverse
protection is not desired remove M2 and connect the
source of M1 directly to V
OUT
.
MOSFET Selection
To protect against a negative voltage at V
IN
, the external
N-channel MOSFETs must be configured in a back-to-
back arrangement. Dual N-channel packages are thus the
best choice. The MOSFET is selected based on its power
handling capability, drain and gate breakdown voltages,
and threshold voltage.
The drain to source breakdown voltage must be higher
than the maximum voltage expected between V
IN
and V
OUT
.
Note that if an application generates high energy transients
during normal operation or during Hot Swap™, the external
MOSFET must be able to withstand this transient voltage.
Due to the high impedance nature of the charge pump that
drives the GATE pin, the total leakage on the GATE pin must
be kept low. The gate drive curves of Figure 2 were measured
with a 1µA load on the GATE pin. Therefore, the leakage on
the GATE pin must be no greater than 1µA in order to match
the curves of Figure 2. Higher leakage currents will result
in lower gate drive. The
dual N-channel MOSFETs shown
in
Table 1 all have a maximum GATE leakage current of
100nA. Additionally, Table 1 lists representative MOSFETs
that would work at different values of V
IN
.
Layout Considerations
The trace length between the V
IN
pin and the drain of the
external MOSFET should be minimized, as well as the trace
length between the GATE pin of the LTC4365 and the gates
of the external MOSFETs.
Place the bypass capacitors at V
OUT
as close as possible
to the external MOSFET. Use high frequency ceramic
capacitors in addition to bulk capacitors to mitigate Hot
Swap ringing. Place the high frequency capacitors closest
to the MOSFET. Note that bulk capacitors mitigate ringing
by virtue of their ESR. Ceramic capacitors have low ESR
and can thus ring near their resonant frequency.
Figure 20. 12V Application Protected from 150V Transients
V
IN
UV
OV
SHDN
OV = 17.9V
D3: SMAJ43CA BI-DIRECTIONAL
4365 F20
V
OUT
FAULT
GATE
M1 M2
V
IN
12V
FDB33N25
V
OUT
GND
LTC4365
R3
510k
D3
R2
2050k
R1
59k
R6
1k