Datasheet

LTC4362-1/LTC4362-2
8
436212fa
APPLICATIONS INFORMATION
ON Input
ON is a CMOS compatible, active low enable input. It has
a default 5µA pull-down to ground. Connect this pin to
ground or leave open to enable normal device operation.
If it is driven high while the MOSFET is turned on, the
MOSFET is turned off gradually with an internal 40µA
gate pull-down, minimizing input voltage transients. The
LTC4362 then goes into a low current sleep mode, draw-
ing only 1.5µA at IN. When ON goes back low, the part
restarts with a 130ms delay cycle.
GATEP Control
GATEP has a 2M resistive pull-down to ground and a
5.8V Zener clamp in series with a 200k resistor to IN.
It controls the gate of an optional external P-channel
MOSFET to provide negative voltage protection. The 2M
pull-down turns on the external P-channel MOSFET once
V
IN
is more than the P-channel MOSFET gate threshold
voltage. The IN to GATEP Zener protects the external P-
channel MOSFET from gate overvoltage by clamping its
V
GS
to 5.8V when V
IN
goes high.
above 1.5V (V
ON(TH)
) for more than 500µs. After reset, the
LTC4362-1 goes through the start-up cycle. In applications
not requiring the overcurrent protection, tie SENSE and
the exposed pad to the IN pin.
PWRGD Output
PWRGD is an active low output with a MOSFET pull-down
to ground and a 500k resistive pull-up to OUT. The PWRGD
pin pull-down releases during the low current sleep mode
(invoked by ON high), UVLO, overvoltage, overcurrent or
thermal shutdown and the subsequent 130ms start-up
delay. After the start-up delay, the internal MOSFET gate
starts its 3V/ms ramp-up and control of the PWRGD
pull-down passes on to the internal gate high compara-
tor. When the internal gate is higher than the gate high
threshold for more than 65ms, PWRGD asserts low. When
the internal gate goes lower than the gate high threshold,
the PWRGD pull-down releases. The PWRGD pull-down
device is capable of sinking up to 3mA of current allowing
it to drive an optional LED. To interface PWRGD to another
I/O rail, connect a resistor from PWRGD to that I/O rail
with a resistance low enough to override the internal 500k
pull-up to OUT. Figure 2 details PWRGD behavior for a
LTC4362-2 with 1k pull-up to 5V at PWRGD.
IN
OUT
INTERNAL
MOSFET
GATE
ON
PWRGD
I
CABLE
10µs
(NOT TO SCALE)
GATE HIGH
THRESHOLD
GATE HIGH
THRESHOLD
OC
THRESHOLD
GATE HIGH
THRESHOLD
GATE HIGH
THRESHOLD
GATE HIGH
THRESHOLD
V
IN(OV)
– ∆V
OV
START-UP
FROM UVLO
RESTART
FROM OV
OV
RESTART
FROM ON
ON
RESTART
FROM OC
OC
130ms
65ms
130ms
65ms
130ms
65ms
130ms
65ms
V
IN(OV)
V
IN(UVL)
436212 F02
Figure 2. PWRGD Behavior