Datasheet
LTC4361-1/LTC4361-2
8
436112fb
applicaTions inFormaTion
The LTC4361-1 has an internal latch that maintains this
off state until it is reset. To reset this latch, cycle IN be-
low 2.1V (V
IN(UVL)
) or ON above 1.5V (V
ON(TH)
) for more
than 500µs. After reset, the LTC4361-1 goes through the
start-up cycle.
In applications not requiring the overcurrent protection, tie
the SENSE pin to the IN pin. To implement an overcurrent
threshold I
TRIP
, choose R
SENSE
using the formula:
R
SENSE
=
∆V
OC
I
TRIP
After choosing the R
SENSE
, keep in mind that:
I
TRIP(MAX)
=
∆V
OC(MAX)
R
SENSE(MIN)
I
TRIP(MIN)
=
∆V
OC(MIN)
R
SENSE(MAX)
PWRGD
Output
PWRGD is an active low output with a MOSFET pull-down
to ground and a 500k resistive pull-up to OUT. The PWRGD
pin pull-down releases during the low current sleep mode
(invoked by ON high), UVLO, overvoltage or overcurrent
and the subsequent 130ms start-up delay. After the start-
up delay, GATE starts its slow ramp-up and control of the
PWRGD pull-down passes on to the GATE high comparator.
V
GATE
> V
GATE(TH)
for more than 65ms asserts the PWRGD
pull-down and V
GATE
< V
GATE(TH)
releases the pull-down.
The PWRGD pull-down is capable of sinking up to 3mA of
current allowing it to drive an optional LED. To interface
PWRGD to another I/O rail, connect a resistor from PWRGD
to the I/O rail with a resistance low enough to override
the internal 500k pull-up to OUT. Figure 2 details PWRGD
behavior for a LTC4361-2 with 1k pull-up to 5V at PWRGD.
IN
OUT
GATE
ON
PWRGD
V
GATE(TH)
V
GATE(TH)
V
GATE(TH)
V
GATE(TH)
V
GATE(TH)
V
IN(UVL)
I
CABLE
OC
THRESHOLD
10µs (NOT TO SCALE)
436112 F02
V
IN(OV)
–∆V
OV
START-UP
FROM UVLO
RESTART
FROM OV
OV
RESTART
FROM ON
ON
RESTART
FROM OC
OC
V
IN(OV)
130ms
65ms
130ms
65ms
130ms
65ms
130ms
65ms
Figure 2. PWRGD Behavior