Datasheet

LTC4290/LTC4271
24
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For more information www.linear.com/LTC4290
ApplicAtions inForMAtion
SERIAL DIGITAL INTERFACE
Overview
The LTC4290/LTC4271 communicates with the host us
-
ing a standard SMBus/I
2
C 2-wire interface. The LTC4290/
LTC4271 is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
Timing Diagrams (Figures 5 through 9) show typical
communication waveforms and their timing relationships.
More information about the SMBus data protocols can be
found at www.smbus.org.
The LTC4290/LTC4271 requires both the V
DD
and V
EE
sup-
ply rails to be present for the serial interface to function.
Bus Addressing
The LTC4290/L
TC4271’s primary 7-bit serial bus address
is A
6
10A
3
A
2
A
1
A
0
b, with bit 6 controlled by AD6 and the
lower four bits set by the AD3-AD0 pins; this allows up to
16 LTC4290/LTC4271s, on a single bus. Sixteen LTC4290/
LTC4271 are equivalent to 32 quad PSEs or 128 ports. All
LTC4290/LTC4271s also respond to the broadcast address
0110000b, allowing the host to write the same command
(typically configuration commands) to multiple LTC4290/
LTC4271s in a single transaction. If the LTC4290/LTC4271
is asserting the INT pin, it will also respond to the alert
response address (0001100b) per the SMBus specification.
Each LTC4290/LTC4271 is logically composed of two quads
of four ports each. Each quad occupies separate, contigu
-
ous I
2
C addresses. The AD6, AD3-0 pins set the address
of the base quad while the second quad is consecutively
numbered. I
2
C addresses outside of the x10xxxxb range
are considered illegal and will not respond. Each internal
quad is independent of the other quad, with the exception
of writes to the Chip Reset, MSD Inversion and General
Purpose Input Output registers. These registers are global
in nature and will affect all quads.
Figure 14. Example I
2
C Bus Addressing
Interrupts and SMBAlert
Most LTC4290/LTC4271 port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host
to poll the LTC4290/LTC4271, minimizing serial bus traf
-
fic and conserving host CPU cycles. Multiple LTC4290/
L
TC4271s can share a common
INT line, with the host
using the SMBAlert protocol (ARA) to determine which
LTC4290/LTC4271 caused an interrupt.
Register Description
For information on serial bus usage and device configura
-
tion and status, refer to the LTC4271 Software Program-
ming documentation.
ISOLATION REQUIREMENTS
IEEE 802.3 Ethernet specifications require that network
segments (including PoE cir
cuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be isolated
from each other, provided that the segments are connected
to devices residing within a single building on a single
power distribution system.
QUAD 0QUAD 1
LTC4271
AD0
AD1
AD2
AD3
AD6
SCL
SDAIN
SDAOUT
SCL
SDA
AD0
3.3V
AD1
AD2
AD3
AD6
SCL
SDAIN
SDAOUT
I
2
C ADDRESS
0100000
0100001
QUAD 0QUAD 1
LTC4271
I
2
C ADDRESS
0100111
0101000
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