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LTC4290/LTC4271

429071fa

For more information www.linear.com/LTC4290

PoE PSE Switches/Routers

PoE PSE Midspans

ApplicAtions

FeAtures

Description

8-Port PoE/PoE

/LTPoE

PSE Controller

The LTC

4290/LTC4271 chipset is an 8-port power sourc-

ing equipment (PSE) controller designed for use in IEEE

802.3at Type 1 and T

ype 2 (high power) compliant Power

over Ethernet (PoE) systems. Transformer-isolated com

munication protocol replaces expensive opto-couplers

and complex isolated 3.3V supply resulting in significant

BOM cost savings. The LTC4290/LTC4271 chipset delivers

lowest-in-industry heat dissipation by utilizing low-R

DS(ON)

external MOSFETs and 0.25Ω sense resistors.

Advanced power management features include per-port 12-

bit current monitoring ADCs, DAC-programmable current

limit, and versatile fast shut-down of preselected ports.

Advanced power management host software is available

under a no-cost license. PD discovery uses a proprietary

dual-mode 4-point detection mechanism ensuring excel

lent immunity from false PD detection. Midspan PSEs

are

supported

with 2-event classification and a 2 second

backoff timer. The LTC4290/LTC4271 includes an I

C serial

interface operable up to 1MHz.

The LTC4290/LTC4271 is available in multiple power grades

allowing delivered PD power up to 90W.

Eight Independent PSE Channels

Compliant with IEEE 802.3at Type 1 and 2

Chipset Provides Electrical Isolation

Reduced BOM Cost

Eliminates up to 6 High Speed Opto-Couplers

Eliminates Isolated 3.3V Power Supply

Low Power Dissipation

0.25Ω Sense Resistance Per Channel

Very High Reliability 4-Point PD Detection

2-Point Forced Voltage

2-Point Forced Current

and V

PORT

Monitoring

1 Second Rolling I

PORT

Averaging

Supports 2-Pair and 4-Pair Output Power

1MHz I

C Compatible Serial Control Interface

Available In Three Power Grades

A-Grade – LTPoE

™ 38.7W to 90W

B-Grade – PoE

25.5W

C-Grade – PoE 13W

Available In a 40-Lead 6mm × 6mm (LTC4290)

and 24-Lead 4mm × 4mm (LTC4271) QFN Package

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

and LTPoE

is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

typicAl ApplicAtion

••

3.3V

3.3V 0.1µF

–54V

100Ω

••

3.3V

1µF

0.1µF

–54V

100Ω

GP0

GP1

MID

RESET

MSD

INT

AUTO

SCL

AD0

AD1

AD2

AD3

AD6

DGND CAP1 CAP2

DND

DPD

CND

CPD

DNA

SENSE1

GATE1

OUT1

LTC4290

DPA

CNA

CPA

XIO0 XIO1

0.22µF

100V

0.22µF

100V

S1B

–54V

429071 TA01a

–54V

S1B

PORTn

PORT1

SDAIN

SDAOUT

LTC4271

NO ISOLATION

REQUIRED ON

C INTERFACE

DD33

2nF 2kV

SENSEn

GATEn

OUTn

AGNDVSSK

0.25Ω

–54V

>47µF

SYSTEM

BULK CAP

LTC4290/LTC4271 FAMILY

LTC4290

GRADE ISOLATION LTPoE

PoE

MAX

DELIVERED

POWER

A Transformer

l l l

90W

B Transformer

l l

25.5W

C Transformer

13W

Summary of content (32 pages)

PAGE 1
LTC4290/LTC4271 8-Port PoE/PoE+/LTPoE++ PSE Controller Features Description Eight Independent PSE Channels n Compliant with IEEE 802.3at Type 1 and 2 n Chipset Provides Electrical Isolation Reduced BOM Cost Eliminates up to 6 High Speed Opto-Couplers Eliminates Isolated 3.3V Power Supply n Low Power Dissipation 0.
PAGE 2
LTC4290/LTC4271 Absolute Maximum Ratings (Notes 1, 4) (Note 1) LTC4290 Supply Voltages AGND – VEE............................................ –0.3V to 80V VSSK (Note 7)...................... VEE – 0.3V to VEE + 0.3V Digital Pins XIOn .................................. VEE – 0.3V to CAP2 + 0.3V Analog Pins SENSEn, GATEn, OUTn ......... VEE – 0.3V to VEE + 80V CAP2 (Note 13) ........................ VEE –0.3V to VEE + 5V CPA, CNA, DPA, DNA...............VEE – 0.3V to VEE + 0.
PAGE 3
LTC4290/LTC4271 Pin Configuration LTC4271 28 OUT8 GATE2 4 27 GATE7 OUT2 5 41 VSSK CAP2 6 CAP1 24 23 22 21 20 19 29 GATE8 OUT1 3 VDD33 30 VEE GATE1 2 AUTO MSD 40 39 38 37 36 35 34 33 32 31 VEE 1 GP1 NC TOP VIEW NC VEE NC NC DNA DPA CNA CPA VEE TOP VIEW GP0 LTC4290 AD0 1 18 SCL AD1 2 17 SDAIN 26 OUT7 AD2 3 25 AGND AD3 4 16 SDAOUT 25 DGND 15 INT 24 GATE6 AD6 5 14 RESET OUT3 8 23 OUT6 MID 6 13 DNC GATE4 9 22 GATE5 VDD33 DND 9 10 11 12 DPD NC XIO1 SENSE8 S
PAGE 4
LTC4290/LTC4271 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 & 4) SYMBOL PARAMETER MIN TYP MAX UNITS AGND – VEE For IEEE Type 1 Compliant Output For IEEE Type 2 Compliant Output For LTPoE++ Compliant Output l l l 45 51 54.75 Undervoltage Lock-Out AGND – VEE l 20 VDD Supply Voltage VDD – DGND l 3.
PAGE 5
LTC4290/LTC4271 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
PAGE 6
LTC4290/LTC4271 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS XIO VOLX XIO Digital Output Low VXIOn – VEE, IXIOn = 5mA l VOHX XIO Digital Output High VXIOn – VEE, IXIOn = 100µA l 0.
PAGE 7
LTC4290/LTC4271 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
PAGE 8
LTC4290/LTC4271 Typical Performance Characteristics 802.3af Power On Sequence in AUTO Pin Mode 0 802.3at Power On Sequence in AUTO Pin Mode 0 AGND FORCED VOLTAGE DETECTION –30 802.3af CLASSIFICATION VEE = –55V CLASS 3 PD POWER ON VEE FORCED CURRENT DETECTION –20 FORCED VOLTAGE DETECTION –30 –40 –50 VEE = –55V CLASS 4 PD 802.
PAGE 9
LTC4290/LTC4271 Typical Performance Characteristics 802.3at ILIM Threshold vs Temperature 208 832 204 –40 –20 0 162 648 160 640 158 632 156 624 154 616 152 –40 –20 816 100 120 20 40 60 80 TEMPERATURE (°C) 656 0 20 40 60 80 TEMPERATURE (°C) DC Disconnect Threshold vs Temperature 802.3at Current Limit Foldback PORT 1 REG 47h = E2h RSENSE = 0.25Ω 7 1.50 6 0 ILIM (mA) 1.
PAGE 10
LTC4290/LTC4271 test Timing Diagrams CLASSIFICATION tDET FORCED-CURRENT VPORTn FORCEDVOLTAGE tME 0V tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE PD CONNECTED tCLEON tPON VEE INT 429071 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes VLIM VCUT VSENSEn TO VEE 0V tSTART, tCUT INT 429071 F02 Figure 2. Current Limit Timing VSENSEn TO VEE VMIN INT tMPS tDIS 429071 F03 Figure 3. DC Disconnect Timing 429071fa 10 For more information www.linear.
PAGE 11
LTC4290/LTC4271 test Timing Diagrams VGATEn VEE tMSD MSD 429071 F04 Figure 4. Shut Down Delay Timing t3 tr t4 tf SCL t2 t5 t6 t7 t8 SDA t1 429071 F05 Figure 5. I2C Interface Timing 429071fa For more information www.linear.
PAGE 12
LTC4290/LTC4271 I2C Timing Diagrams SCL SDA AD6 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 START BY MASTER A6 A5 A4 A3 A2 ACK BY SLAVE FRAME 1 SERIAL BUS ADDRESS BYTE A0 ACK D7 A1 D6 D5 D4 D3 D2 ACK BY SLAVE D1 D0 ACK STOP BY MASTER ACK BY SLAVE FRAME 2 REGISTER ADDRESS BYTE FRAME 3 DATA BYTE 429071 F06 Figure 6.
PAGE 13
LTC4290/LTC4271 Pin Functions LTC4290 VEE (Pins 1, 30, 33, 40): Main PoE Supply Input. Connect to a –45V to –57V supply, relative to AGND. Voltage depends on PSE type (Type 1, Type 2 or LTPoE++). GATEn (Pins 2, 4, 7, 9, 22, 24, 27, 29): Port n Gate Drive. GATEn should be connected to the gate of the external MOSFET for port n. When the MOSFET is turned on, the gate voltage is driven to 12V (typ) above VEE.
PAGE 14
LTC4290/LTC4271 Pin Functions CND (Pin 9): Clock Transceiver Negative Input Output (Digital). Connect to CNA through a data transformer. DPD (Pin 10): Data Transceiver Positive Input Output (Digital). Connect to DPA through a data transformer. DND (Pin 11): Data Transceiver Negative Input Output (Digital). Connect to DNA through a data transformer. VDD33 (Pins 12, 20): VDD IO Power Supply. Connect to a 3.3V power supply relative to DGND. VDD33 must be bypassed to DGND near the LTC4271 with at least a 0.
PAGE 15
LTC4290/LTC4271 Applications Information OVERVIEW Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial specification was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.
PAGE 16
LTC4290/LTC4271 Applications Information The LTC4290/LTC4271 chipset implements a proprietary isolation scheme for inter-chip communication. This architecture dramatically reduces BOM cost by replacing expensive opto-isolators and isolated power supplies with a single low-cost transformer. connected to the cable, the PSE detects this signature resistance and turns on the power. When the PD is later disconnected, the PSE senses the open circuit and turns power off.
PAGE 17
LTC4290/LTC4271 Applications Information Extended Power LTPoE++ OPERATING MODES A-grade LTC4290/LTC4271 parts add the capability to autonomously deliver up to 90W of power to the PD. LTPoE++ PDs may forgoe 802.3 LLDP support and rely solely on the LTPoE++ Physical Classification to negotiate power with LTPoE++ PSEs; this greatly simplifies highpower PD implementations.
PAGE 18
LTC4290/LTC4271 Applications Information Reset and the AUTO/MID Pins The initial LTC4290/LTC4271 configuration depends on the state of the AUTO and MID pins during reset. Reset occurs at power-up, or whenever the RESET pin is pulled low or the global Reset All bit is set. Changing the state of AUTO or MID after power-up will not properly change the port behavior of the LTC4290/LTC4271 until a reset occurs.
PAGE 19
LTC4290/LTC4271 Applications Information Table 4. Detection Status MEASURED PD SIGNATURE DETECTION RESULT Incomplete or Not Yet Tested Detect Status Unknown < 2.4k Short Circuit Capacitance > 2.7µF CPD too High 2.
PAGE 20
LTC4290/LTC4271 Applications Information current level indicating one of 5 possible PD classes. Figure 13 shows a typical PD load line, starting with the slope of the 25k signature resistor below 10V, then transitioning to the classification signature current (in this case, Class 3) in the VCLASS range. Table 5 shows the possible classification values. Table 5. 802.3af and 802.
PAGE 21
LTC4290/LTC4271 Applications Information the Port Status register will always report the results of the last class pulse, so an invalid Class 4–Class 2 combination would report a second class pulse was run in the High Power Status register (which implies that the first cycle found class 4), and Class 2 in the Port Status register. POWER CONTROL The primary function of the LTC4290/LTC4271 is to control the delivery of power to the PSE port.
PAGE 22
LTC4290/LTC4271 Applications Information Table 6. Example Current Limit Settings INTERNAL REGISTER SETTING (hex) ILIM (mA) RSENSE = 0.5Ω 53 88 106 08 159 89 213 80 266 8A 319 09 372 8B 425 00 478 8E 531 92 584 CB RSENSE = 0.
PAGE 23
LTC4290/LTC4271 Applications Information Port Current Policing Masked Shutdown The LTC4290/LTC4271 can augment tCUT current monitoring with a policing function to track the one second current averages. A port violating the user-specified Port Police Threshold will be shut off with both a tCUT and Police event recorded.
PAGE 24
LTC4290/LTC4271 Applications Information SERIAL DIGITAL INTERFACE I2C ADDRESS I2C ADDRESS The LTC4290/LTC4271 requires both the VDD and VEE supply rails to be present for the serial interface to function. 0100001 AD0 AD1 AD2 AD3 AD6 SCL SDAIN SDAOUT QUAD 0 0100000 3.3V 0100111 QUAD 1 AD0 AD1 AD2 AD3 AD6 QUAD 0 The LTC4290/LTC4271 communicates with the host using a standard SMBus/I2C 2-wire interface.
PAGE 25
LTC4290/LTC4271 Applications Information For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main power supply for the entire device. This strategy can be used if the device has no electrically conducting ports other than twisted-pair Ethernet. In this case, the SDAIN and SDAOUT pins can be tied together and will act as a standard I2C/SMBus SDA pin.
PAGE 26
LTC4290/LTC4271 Applications Information 3.3V NO ISOLATION REQUIRED ON I2C INTERFACE 0.1µF XIO0 VDD33 GP0 GP1 100Ω 3.3V • • 100Ω SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 CPA CPD MID RESET MSD AUTO INT 0.25Ω SENSEn CNA • • 100Ω LTC4290 100Ω 0.22µF 100V 100Ω S1B GATE1 CAP2 VEE 2nF, 2kV S1B PORT1 DNA T2 –54V OUT1 –54V CAP1 1µF S1B DPA 3.3V DGND PORTn GATEn –54V T1 100Ω S1B 100Ω DPD DND 0.22µF 100V OUTn 100Ω CND LTC4271 XIO1 VSSK AGND SENSE1 0.1µF 1µF –54V 0.
PAGE 27
LTC4290/LTC4271 Applications Information ESD/Cable Discharge Protection LAYOUT GUIDELINES Ethernet ports can be subject to significant ESD events when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the RJ45 jack. To protect against damage, each port requires a pair of clamp diodes; one to AGND and one to VEE (Figure 16). An additional surge suppressor is required for each LTC4290 chip from VEE to AGND.
PAGE 28
1µF DND CND DPD CPD 0.1µF DGND CAP1 VDD33 GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 3.3V 100Ω 3.3V 100Ω 100Ω 3.3V 100Ω 1µF T3 T2 • • 2nF 2000V SMAJ58A • • 1µF –54V –54V OUT1 GATE1 SENSE1 For more information www.linear.com/LTC4290 –54V + (NETWORK PHYSICAL LAYER CHIP) • • • –54V ISOLATED ISOLATED GND • PHY RS S1B 0.22µF 100V X7R T1 S1B • • • • 0.25Ω, 1% FDMC3612 0.
PAGE 29
LTC4290/LTC4271 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) R = 0.115 TYP 0.75 0.05 PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45º CHAMFER 23 24 0.40 0.10 1 2 2.
PAGE 30
LTC4290/LTC4271 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 0.
PAGE 31
LTC4290/LTC4271 Revision History REV DATE DESCRIPTION A 4/13 Added A-grade and C-grade to entire data sheet PAGE NUMBER 1 - 32 429071fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LTC4290 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 32
LTC4290/LTC4271 Typical Application Complete 8-Port PSE 3.3V 0.1µF 1µF 7 VDD33 GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 XIO0 CPA CPD 100Ω 3.3V • • 100Ω 100Ω 3.3V • LTC4290 CNA DPA • 100Ω RJ45 CONNECTOR 1µF 100V X7R SMAJ58A S1B • 0.1µF T1 • >47µF SYSTEM BULK CAP + • (NETWORK PHYSICAL LAYER CHIP) • –54V • 0.01µF 200V 75Ω • • • ISOLATED GND PHY • –54V ISOLATED 2nF 2000V • • 1µF RS DNA AGND CAP2 VEE VSSK 2 0.22µF 100V X7R 0.