Datasheet

LTC4280
18
4280f
APPLICATIONS INFORMATION
of R5 resistance, the absence of a drain bypass capacitor,
a combination of bus wiring inductance and bus supply
output impedance. To prevent this second type of oscillation
avoid load capacitance below 10µF, alternately connect an
external capacitor from the MOSFET gate to ground with
a value greater than 1.5µF.
Supply Transients
The LTC4280 is designed to ride through supply transients
caused by load steps. If there is a shorted load and the
parasitic inductance back to the supply is greater than
0.5µH, there is a chance that the supply collapses before
the active current limit circuit brings down the GATE pin.
If this occurs, the undervoltage monitors pull the GATE
pin low. The undervoltage lockout circuit has a 2µs fi lter
time after V
DD
drops below 2.74V. The UV pin reacts in
2µs to shut the GATE off, but it is recommended to add a
fi lter capacitor C
F
to prevent unwanted shutdown caused
by a transient. Eventually either the UV pin or undervoltage
lockout responds to bring the current under control before
the supply completely collapses.
Supply Transient Protection
The LTC4280 is safe from damage with supply voltages up
to 24V. However, spikes above 24V may damage the part.
During a short-circuit condition, large changes in current
fl owing through power supply traces may cause inductive
voltage spikes which exceed 24V. To minimize such spikes,
the power trace inductance should be minimized by using
wider traces or heavier trace plating. Also, a snubber circuit
dampens inductive voltage spikes. Build a snubber by using
a 100Ω resistor in series with a 0.1µF capacitor between
V
DD
and GND. A surge suppressor, Z1 in Figure 1, at the
input can also prevent damage from voltage surges.
Design Example
As a design example, take the following specifi cations:
V
IN
= 12V, I
MAX
= 5A, I
INRUSH
= 1A, 5ms FILTER time,
C
L
= 330µF, V
UV(ON)
= 10.75V, V
OV(OFF)
= 14.0V, V
PWRGD(UP)
= 11.6V, and I
2
C ADDRESS = 1010011. This completed
design is shown in Figure 1.
Selection of the sense resistor, R
S
, is set by the overcurrent
threshold of 25mV:
R
mV
I
S
MAX
==
25
0 005. Ω
The MOSFET is sized to handle the power dissipation during
inrush when output capacitor C
OUT
is being charged. A
method to determine power dissipation during inrush is
based on the principle that:
Energy in CL = Energy in Q1
This uses:
Energy in C
L
==
()()
1
2
1
2
033 12
2
2
CV mF.
or 0.024 joules. Calculate the time it takes to charge up
C
OUT
:
tC
V
I
mF
V
A
ms
STARTUP L
DD
INRUSH
== =•.•033
12
1
4
The power dissipated in the MOSFET:
P
t
W
DISS
STARTUP
==
Energyin C
L
6
The SOA (safe operating area) curves of candidate MOSFETs
must be evaluated to ensure that the heat capacity of the
package tolerates 6W for 4ms. The SOA curves of the
Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,
satisfying this requirement. Since the FDC653N has less
than 8µF of gate capacitance and we are using a GATE
RC network, the short-circuit stability of the current limit
should be checked and improved by adding a capacitor
from GATE to SOURCE if needed.
The inrush current is set to 1A using C1:
CC
I
I
CmF
μA
A
or C
L
GATE
INRUSH
1
1033
20
1
16
=
==
•
.•.88nF