Datasheet

LTC4280
14
4280f
APPLICATIONS INFORMATION
When the MOSFET is turning on, the inrush current follows
the foldback profi le as shown in Figure 2. Meanwhile the
FILTER pin is held low with 0.6mA to prevent the FILTER
pin from generating an overcurrent fault during start-up.
The TIMER pin integrates at 100µA during start-up and
once it reaches its threshold of 1.235V, the part checks
to see if it is in current limit, which indicates that it has
started up into a short-circuit condition. If this is the case,
the overcurrent fault bit, D2 in Table 5, is set and the part
turns off. If the part is not in current limit, the FILTER pin
is released to enable circuit breaker and current limit based
overcurrent faults. Alternately an internal 100ms start-up
timer may be selected by tying the TIMER pin to INTV
CC
.
a 20µA pull-up current from the gate pin slews the gate
upwards and the part is not in current limit. The start-up
TIMER may expire in this condition and an OC fault is not
generated even though start-up has not completed. Either
the sense voltage increases to the 25mV CB threshold or
the current limit as set by the FB pin which generates an
OC fault when the FILTER pin reaches its 1.235V threshold,
or the FB pin voltage crosses its 1.235V power good
threshold and the GPIO pin signals power good.
GATE Pin Voltage
A curve of gate-to-source drive vs V
DD
is shown in the
Typical Performance Characteristics. At minimum input
supply voltage of 2.9V, the minimum gate-to-source drive
voltage is 4.7V. The gate-to-source voltage is clamped
below 6.5V to protect the gates of logic level N-channel
MOSFETs.
Turn-Off Sequence
The GATE is turned off by a variety of conditions. A normal
turn-off is initiated by the ON pin going low or a serial bus
turn-off command. Additionally, several fault conditions
turn off the GATE. These include an input overvoltage
(OV pin), input undervoltage (UV pin), overcurrent circuit
breaker (SENSE
–
pin), or EN transitioning high. Writing
a logic one into the UV, OV or OC fault bits (D0-D2 in
Table 5) also latches off the GATE if their auto-retry bits
are set to false.
Normally the MOSFET is turned off with a 1mA current
pulling down the GATE pin to ground. With the MOSFET
turned off, the SOURCE and FB voltages drop as C
L
discharges. When the FB voltage crosses below its
threshold, GPIO pulls low to indicate that the output power
is no longer good.
If the V
DD
pin falls below 2.74V for greater than 2µs or
INTV
CC
drops below 2.60V for greater than 1µs, a fast shut
down of the MOSFET is initiated. The GATE pin is pulled
down with a 450mA current to the SOURCE pin.
V
DD
+ 6V
V
GATE
V
OUT
GPIO1
(POWER GOOD)
I
LOAD
• R
SENSE
V
DD
V
SENSE
25mV
10mV
FB
LIMITED
4280 F02
TIMER
EXPIRES
t
STARTUP
Figure 2. Power-Up Waveforms
As the SOURCE voltage rises, the FB pin follows as set
by R7 and R8. Once FB crosses its 1.235V threshold, and
the start-up timer has expired, the GPIO pin, in its default
confi guration, ceases to pull low and indicates that power
is now good.
If R6 and C1 are employed for a constant current during
start-up, which produces a constant dV/dt at the output,