LTC4280 Hot Swap Controller with 2 I C Compatible Monitoring FEATURES DESCRIPTION n The LTC®4280 Hot Swap™ controller allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, board supply voltage and inrush current are ramped up at an adjustable rate. An I2C interface and onboard ADC allow for monitoring of load current, voltage and fault status.
LTC4280 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) SOURCE GATE SENSE– SENSE+ VDD TOP VIEW 24 23 22 21 20 UV 1 19 FB OV 2 18 GPIO FILTER 3 17 INTVCC 25 GND 4 16 TIMER ON 5 15 ADIN EN 6 14 ADR2 13 ADR1 NC ADR0 9 10 11 12 ALERT 8 SCL SDAO 7 SDAI Supply Voltage (VDD) ................................. –0.3V to 24V Supply Voltage (INTVCC) ........................... –0.3V to 6.5V Input Voltages GATE-SOURCE (Note 3) ........................... –0.3V to 5V SENSE+, SENSE– ......
LTC4280 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VDD Input Supply Range l 2.
LTC4280 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.25 0.
LTC4280 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC –0.8 INTVCC –0.4 INTVCC –0.2 V –3 μA μA 0.8 V I2C Interface VADR(H) ADR0, ADR1, ADR2 Input High Voltage IADR(IN,Z) ADR0, ADR1, ADR2 Hi-Z Input Current VADR(L) l l l 3 ADR0, ADR1, ADR2 Input Low Voltage l 0.2 –80 ADR0, ADR1, ADR2 = 0.
LTC4280 TYPICAL PERFORMANCE CHARACTERISTICS IDD vs VDD TA = 25°C, VDD = 12V unless otherwise noted INTVCC vs VDD INTVCC vs ILOAD 4.0 4 4 VDD = 12V, 5V 3 3 VDD = 3.3V 2 VCC (V) VDD (V) IDD (mA) 3.5 2 3.0 1 1 2.5 0 0 15 10 VDD (V) 5 20 25 0 3.0 2.5 3.5 VTH(UV) vs Temperature 1.234 ITIMER vs Temperature 90 110 85 105 ITIMER (μA) VHYST(UV) (mV) VTH (UV) RISING (V) 1.238 80 –25 50 25 0 TEMPERATURE (°C) 70 –50 100 75 –25 50 25 0 TEMPERATURE (°C) 75 4280 G04 15 10 5 0.
LTC4280 TYPICAL PERFORMANCE CHARACTERISTICS ΔVGATE vs Temperature ΔVGATE vs IGATE 6.1 IGATE Pull-Up vs Temperature –30 7 VDD = 5V –25 5 $VGATE (V) 5.9 VDD = 5V 6 VDD = 12V 5.8 5.7 VDD = 12V IGATE (μA) 6.0 $VGATE(SOURCE) (V) TA = 25°C, VDD = 12V unless otherwise noted 4 VDD = 3.3V 3 –20 VDD = 3.3V 5.6 2 5.5 1 5.
LTC4280 PIN FUNCTIONS ADIN: ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to ground if unused. ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying these pins to ground, to the INTVCC pin or open configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register.
LTC4280 PIN FUNCTIONS SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller. An external pull-up resistor or current source is required. SOURCE: N-Channel MOSFET Source and ADC Input. Connect this pin to the source of the external N-channel MOSFET switch for gate drive return. This pin also serves as the ADC input to monitor output voltage.
LTC4280 FUNCTIONAL DIAGRAM SENSE– CB FOLDBACK 1.235V 0.6V FB 1.235V UV 0.4V OV INTVCC EN 1.235V 10μA 1.235V UV RST RESET + – OV1 1.235V 2.84V 15.6V + – + – + – – + +– GATE CS CHARGE PUMP AND GATE DRIVER SOURCE 26mV 25mV FET ON UV + – + – + – –+ FAULT 1.235V + – PG 10μA FILTER PWRGD 1.235V 2μA FAULT GP OV LOGIC EN ON ON UVLO1 VDD(UVLO) TM2 + – GPI0 1V + – 0.2V 100μA TIMER 2μA 3.1V GEN 1.
LTC4280 TIMING DIAGRAM SDAI/SDAO tSU, DAT tHD, DATO, tHD, DATI tSU, STA tSP tHD, STA tSP tBUF tSU, STO 4280 TD01 SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION 4280f 11
LTC4280 OPERATION The LTC4280 is designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate driver turn on an external N-channel MOSFET’s gate to pass power to the load. The gate driver uses a charge pump that derives its power from the VDD pin. Also included in the gate driver is an internal 6.5V gate-to-source clamp.
LTC4280 APPLICATIONS INFORMATION A typical LTC4280 application is in a high availability system in which a positive voltage supply is distributed to power individual cards. The device measures card voltages and currents and records past and present fault conditions. The system queries each LTC4280 over the I2C periodically and reads status and measurement information. A basic LTC4280 application circuit is shown in Figure 1.
LTC4280 APPLICATIONS INFORMATION When the MOSFET is turning on, the inrush current follows the foldback profile as shown in Figure 2. Meanwhile the FILTER pin is held low with 0.6mA to prevent the FILTER pin from generating an overcurrent fault during start-up. The TIMER pin integrates at 100μA during start-up and once it reaches its threshold of 1.235V, the part checks to see if it is in current limit, which indicates that it has started up into a short-circuit condition.
LTC4280 APPLICATIONS INFORMATION Overcurrent Fault The LTC4280 features an adjustable current limit that protects against short-circuits or excessive load current until an overcurrent fault is generated. An overcurrent fault can occur in two different manners. First, at the end of start-up when the TIMER pin reaches its 1.235V threshold or the internal 100ms start-up timer expires, if the part is in current limit an overcurrent fault is generated.
LTC4280 APPLICATIONS INFORMATION If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4280 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the EN pin detects when the plug-in card is removed. Figure 4 shows an example where the EN pin is used to detect insertion. Once the plug-in card is reinserted the fault register is cleared (except for D4).
LTC4280 APPLICATIONS INFORMATION pin or bit A3 going from high to low, if the UV pin is brought below its 0.4V reset threshold for 2μs, or if INTVCC falls below its 2.64V undervoltage lockout threshold. Finally, when EN is brought from high to low, only FAULT bits D0-D3 are cleared, and bit D4, that indicates a EN change of state, is set. Note that faults that are still present, as indicated in STATUS Register C, cannot be cleared. The FAULT register is not cleared when auto-retrying.
LTC4280 APPLICATIONS INFORMATION of R5 resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output impedance. To prevent this second type of oscillation avoid load capacitance below 10μF, alternately connect an external capacitor from the MOSFET gate to ground with a value greater than 1.5μF. Supply Transients The LTC4280 is designed to ride through supply transients caused by load steps.
LTC4280 APPLICATIONS INFORMATION For a start-up time of 4ms with a 2x safety margin we choose: t STARTUP 12.3ms/μF 8ms C TIMER = ≅ 0.68μF 12.3ms/μμF Layout Considerations VUV(ON) • R3 • UVTH(RISING) OVTHH(FALLING) VUV(ON) • (R3 + R2) UVTH(RISING) – R3 – R3 – R2 The FB divider is solved by picking R8 and solving for R7, choosing 3.57kΩ for R8 we get: R7 = VPWRGD(UP) • R8 FBTH(RISING) ILOAD SENSE RESISTOR RS In our case we choose R3 to be 3.4kΩ to give a resistor string current below 100μA.
LTC4280 APPLICATIONS INFORMATION SDA a6 - a0 SCL 1-7 b7 - b0 8 9 1-7 b7 - b0 8 9 1-7 8 9 P S START CONDITION ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION 4280 F06 Figure 6. Data Transfer Over I2C or SMBus Digital Interface I2C Device Addressing The LTC4280 communicates with a bus master using a 2-wire interface compatible with I2C Bus and SMBus, an I2C extension for low power devices.
LTC4280 APPLICATIONS INFORMATION remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master may abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master pulls down the SDA line during the clock pulse to indicate receipt of the data.
LTC4280 APPLICATIONS INFORMATION S ADDRESS W A 0 0 1 0 a4:a0 COMMAND A DATA A P X X X X X b2:b0 FROM MASTER TO SLAVE 0 b7:b0 0 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION FROM SLAVE TO MASTER 4280 F07 Figure 7. LTC4280 Serial Bus SDA Write Byte Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND A DATA A DATA X X X X X b2:b0 0 b7:b0 0 XXXXXXXX A P 0 4280 F08 Figure 8.
LTC4280 APPLICATIONS INFORMATION Table 1.
LTC4280 APPLICATIONS INFORMATION Table 2.
LTC4280 APPLICATIONS INFORMATION Table 4.
LTC4280 TYPICAL APPLICATIONS 5V Backplane Resident Application with Insertion Activated Turn-On and a 5A Circuit Breaker RS 0.005Ω VIN 5V R1 11.5k 1% CF 0.1μF R5 10Ω R2 1.74k 1% R3 2.67k 1% Q1 FDD3706 UV VDD SENSE+ SENSE– GATE SOURCE FB OV ON GPIO SDAI EN LTC4280UFD SDAO ADIN SCL ALERT FILTER INTVCC TIMER ADR0 ADR1 ADR2 GND R7 6.98k 1% R8 2.67k 1% VOUT 5V R4 100k LOAD CEN 1μF CF 47nF C3 0.
LTC4280 PACKAGE DESCRIPTION UFD Package 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696 Rev A) 0.70 p 0.05 4.50 p 0.05 3.10 p 0.05 2.00 REF 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 3.00 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) R = 0.05 TYP 2.00 REF R = 0.115 TYP 23 0.75 p 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 24 0.40 p 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.
LTC4280 TYPICAL APPLICATION –12V Card Resident Application with Optically Isolated I2C and a 16.6A Circuit Breaker RS 0.0015Ω Q1 Si7880DP OUTPUT GND –7V R10 3.3k –7V 5V 2 8 R9 10k 6 CF 0.1μF 3 HCPL-0300 5 –12V SDA R4 3.3k 6 8 R2 1.18k 1% R6 15k R3 3.4k 1% UV VDD SENSE + – SENSE GATE R7 30.1k 1% SOURCE FB OV R8 3.57k 1% ADIN LTC4280UFD GPIO EN CL 1000μF FILTER ADR0 INTVCC ADR1 ADR2 GND TIMER –7V C3 0.1μF R12 10k R13 3.
