Datasheet

LTC4274
23
4274fd
APPLICATIONS INFORMATION
V
DD
provides power for most of the internal LTC4274
circuitry, and draws a maximum of 3mA. A ceramic de-
coupling cap of at least 0.1F should be placed from V
DD
to DGND, as close as practical to each LTC4274 chip.
Figure 16 shows a three component low dropout regulator
for a negative supply to DGND generated from the negative
V
EE
supply. V
DD
is tied to AGND and DGND is negative
referenced to AGND. This regulator drives a single LTC4274
device. In Figure 17, DGND is tied to AGND in this boost
converter circuit for a positive V
DD
supply of 3.3V above
AGND. This circuit can drive multiple LTC4274 devices
and opto couplers.
V
EE
is the main supply that provides power to the PD.
Because it supplies a relatively large amount of power and
is subject to significant current transients, it requires more
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set V
EE
near maximum
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the
line regulation specs of the particular power supply used.
Bypass capacitance between AGND and V
EE
is very impor-
tant for reliable operation. If a short circuit occurs at the
output port it can take as long as 1s for the LTC4274 to
begin regulating the current. During this time the current
is limited only by the small impedances in the circuit and
a high current spike typically occurs, causing a voltage
transient on the V
EE
supply and possibly causing the
LTC4274 to reset due to a UVLO fault. A 1F, 100V X7R
capacitor placed near the V
EE
pin is recommended to
minimize spurious resets.
Isolating the Serial Bus
The LTC4274 includes a split SDA pin (SDAIN and SD-
AOUT) to ease opto-isolation of the bidirectional SDA line.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface de-
vice. However, network segments are not required to be
Figure 17. Positive V
DD
Boost Converter
Figure 16. Negative LDO to DGND
4274 F17
R54
56k
C79
2200pF
GND
ITH/RUN
LTC3803
V
CC
2
5
V
FB
1
3
NGATE
Q15
FDC2512
Q13
FMMT723
Q14
FMMT723
SENSE
6
4
V
EE
C74
100µF
6.3V
C75
10µF
16V
L3
100µH
SUMIDA CDRH5D28-101NC
R51
4.7k
1%
R53
4.7k
1%
R52
3.32k
1%
3.3V AT 400mA
R55
806
1%
R59
0.100
1%, 1W
R56
47.5k
1%
R57
1k
D28
B1100
R58
10
R60
10
C73
10µF
6.3V
L4
10µH
SUMIDA CDRH4D28-100NC
+
C77
0.22µF
100V
C78
0.22µF
100V
C76
10µF
63V
4274 F16
R5
750k
D1
CMHZ4687-4.3V
C1
0.1µF
Q2
CMPTA92
V
EE
V
DD
LTC4274
AGND
V
EE
AGND
DGND