Datasheet
LTC4274
10
4274fd
TEST TIMING DIAGRAMS
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes
Figure 2. Current Limit Timing
Figure 3. DC Disconnect Timing
Figure 4. Shut Down Delay Timing Figure 5. I
2
C Interface Timing
V
PORT
INT
t
DETDLY
V
OC
V
EE
t
DET
t
ME1
t
ME2
V
MARK
V
CLASS
15.5V
20.5V
t
CLE1
t
CLE2
t
CLE3
PD
CONNECTED
0V
4274 F01
FORCED-CURRENT
CLASSIFICATION
t
PON
FORCED-
VOLTAGE
V
LIM
V
CUT
0V
V
SENSE
TO V
EE
INT
4274 F02
t
START
, t
ICUT
V
MIN
V
SENSE
TO V
EE
INT
t
DIS
t
MPS
4274 F03
V
GATE
V
EE
MSD or
SHDN
t
SHDN
t
MSD
4274 F04
SCL
SDA
t
1
t
2
t
3
t
r
t
f
t
5
t
6
t
7
t
8
t
4
4274 F05