Datasheet

LTC4270/LTC4271
14
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CPD (Pin 8): Clock Transceiver Positive Input Output
(Digital). Connect to CPA through a data transformer.
CND (Pin 9): Clock Transceiver Negative Input Output
(Digital). Connect to CNA through a data transformer.
DPD (Pin 10): Data Transceiver Positive Input Output
(Digital). Connect to DPA through a data transformer.
DND (Pin 11): Data Transceiver Negative Input Output
(Digital). Connect to DNA through a data transformer.
V
DD33
(Pins 12, 20): V
DD
IO Power Supply. Connect to
a 3.3V power supply relative to DGND. V
DD33
must be
bypassed to DGND near the LTC4271 with at least a 0.1μF
capacitor.
RESET (Pin 14): Reset Input, Active Low. When the RESET
pin is low, the LTC4270/LTC4271 is held inactive with all
ports off and all internal registers reset to their power-up
states. When RESET is pulled
high, the LTC4271 begins
normal operation. RESET can be connected to an external
capacitor or RC network to provide a power turn-on delay.
Internal filtering of the RESET pin prevents glitches less
than 1μs wide from resetting the LTC4270/LTC4271.
Internally pulled up to V
DD
.
INT (Pin 15): Interrupt Output, Open Drain. INT will pull
low when any one of several events occur in the
LTC4271.
It will return to a high impedance state when bits 6 or 7
are set in the Reset PB register (1Ah). The INT signal can
be used to generate an interrupt to the host processor,
eliminating the need for continuous software polling. In-
dividual INT events can be disabled using the INT Mask
register (01h). See LTC4271 Software Programming
documentation for more information. The INT pin is
only
updated between I
2
C transactions.
SDAOUT (Pin 16): Serial Data Output, Open Drain Data
Output for the I
2
C Serial Interface Bus. The LTC4271 uses
two pins to implement the bidirectional SDA function to
simplify optoisolation of the I
2
C bus. To implement a stan-
dard bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
SDAIN (Pin 17): Serial Data Input.
High impedance data
input for the I
2
C serial interface bus. The LTC4271 uses two
pins to implement the bidirectional SDA function to simplify
optoisolation of the I
2
C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
SCL (Pin 18): Serial Clock Input. High impedance clock
input for the I
2
C serial interface bus. The SCL pin should
be connected directly to the I
2
C SCL bus line. SCL must
be tied high if the I
2
C serial interface bus is not used.
CAP1 (Pin 19): Core Power Supply Bypass Capacitor. Con-
nect a 1µF Bypass capacitance to DGND for the internal
1.8V regulator. Do not use other capacitor values.
AUTO (Pin 21): AUTO Pin Mode Input. AUTO pin mode
allows the LTC4271
to detect and power up a PD even if
there is no host controller present on the I
2
C bus. The
AUTO pin determines the state of the internal registers
when the LTC4271 is reset or comes out of V
DD
UVLO
(see LTC4271 Software Programming documentation). The
states of these register bits can subsequently be changed
via the I
2
C interface. Internally pulled down to DGND. Must
be tied locally to either V
DD
or DGND.
GP1 (Pin 22): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
GP0 (Pin 23): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
MSD (Pin 24): Maskable Shutdown Input. Active low.
When pulled low, all ports that have their corresponding
mask bit set in the mconfig register (17h) will be reset.
Internal filtering
of the MSD pin prevents glitches less
than 1μs wide from resetting ports. The MSD Pin Mode
register can configure the MSD pin polarity. Internally
pulled up to V
DD
.
DGND (Exposed Pad Pin 25): Digital Ground. DGND should
be connected to the return from the V
DD
supply.
PIN FUNCTIONS