LTC4268-1 High Power PD With Synchronous No-Opto Flyback Controller Description Features n n n n n n n n n n n Robust 35W PD Front End IEEE 802.
LTC4268-1 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) VPORTN Voltage........................................... 0.3V to –90V VNEG Voltage...................VPORTN + 90V to VPORTN –0.3V VCC to GND Voltage (Note 3) Low Impedance Source.......................... –0.3V to 18V Current Fed...........................................30mA into VCC RCLASS, ILIM_EN Voltage...VPORTN + 7V to VPORTN – 0.3V SHDN Voltage................ VPORTN + 90V to VPORTN – 0.
LTC4268-1 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. SYMBOL PARAMETER CONDITIONS VPORT Supply Voltage Voltage With Respect to VPORTP Pin (Notes 6, 7, 8, 9, 10) IEEE 802.
LTC4268-1 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
LTC4268-1 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. SYMBOL PARAMETER CONDITIONS ILCOMP Feedback Pin Load Compensation Current VRCMP With VSENSE+ = 0V MIN 20 µA VLCOMP Load Comp to VSENSE Offset Voltage VSENSE+ = 20mV, VFB = 1.
LTC4268-1 Typical Performance Characteristics Input Current vs Input Voltage 25k Detection Range 0.5 Input Current vs Input Voltage 100 TA = 25°C 0.2 0.1 CLASS 5* 60 CLASS 4 40 CLASS 3 CLASS 2 CLASS 1 20 0 –2 –4 –6 INPUT VOLTAGE (V) –8 0 –10 42681 G01 CLASS 1 OPERATION 11.5 INPUT CURRENT (mA) 0.3 0 TA = 25°C 80 INPUT CURRENT (mA) INPUT CURRENT (mA) 0.4 Input Current vs Input Voltage 12.0 85°C 10.5 –40°C 10.0 9.5 CLASS 0 0 11.
LTC4268-1 Typical Performance Characteristics VCC(ON) and VCC(OFF) vs Temperature VCC Start-Up Current vs Temperature 16 10 300 VCC(ON) 15 9 250 14 11 150 8 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 4 0 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 42681 G10 100 98 96 94 104 205 200 195 –25 0 50 75 25 TEMPERATURE (°C) 90 –50 125 1.237 VFB (V) 1.236 1.235 1.234 1.233 1.232 1.231 100 125 42681 G16 50 25 0 75 TEMPERATURE (°C) 100 125 VFB Reset vs Temperature 1.04 RCMP OPEN 1.
LTC4268-1 Typical Performance Characteristics 70 125°C 25°C 50 65 IVCMP (µA) –10 1050 1000 55 50 –30 950 45 –50 –70 1100 SINK CURRENT VFB = 1.4V 60 10 Feedback Amplifier gm vs Temperature SOURCE CURRENT VFB = 1.1V –40°C 30 IVCMP (µA) Feedback Amplifier Source and Sink Current vs Temperature gm (µmho) 70 Feedback Amplifier Output Current vs VFB 0.9 1 1.1 1.2 VFB (V) 1.3 40 –50 1.5 1.4 –25 50 25 75 0 TEMPERATURE (°C) 100 42681 G19 3.6 1550 3.
LTC4268-1 Typical Performance Characteristics VCC Clamp Voltage vs Temperature 21.5 Minimum PG On Time vs Temperature 340 ICC = 10mA RtON(MIN) = 158k 330 21.0 tON(MIN) (ns) 320 VCC (V) 20.5 20.0 310 300 290 280 19.5 270 19.0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 260 –50 125 –25 0 50 75 25 TEMPERATURE (°C) Enable Delay Time vs Temperature PG Delay Time vs Temperature 325 300 250 RENDLY = 90k 305 RPGDLY = 27.
LTC4268-1 Pin Functions SHDN (Pin 1): Shutdown Input. Used to command the LTC4268-1 to present an invalid signature and remain inactive. Connecting SHDN to VPORTP lowers the signature resistance to an invalid value and disables the LTC4268-1 PD interface operations. If unused, tie SHDN to VPORTN. NC (Pin 2): No Internal Connection. RCLASS (Pin 3): Class Select Input. Used to set the current the LTC4268-1 maintains during classification. Connect a resistor between RCLASS and VPORTN. (See Table 2.
LTC4268-1 Pin Functions ance of the upper divider resistor. The user can control the amount of hysteresis by adjusting the impedance of the divider. Tie the UVLO pin to VCC if you are not using this function. See the Applications Information for details. This pin is used for the UVLO function of the switching regulator. The PD interface section has an UVLO defined by the IEEE 802.3af specification. SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs.
LTC4268-1 Block Diagram CLASSIFICATION CURRENT LOAD SHDN 1 VPORTP + 1.237V 16k 2 NC – RCLASS 3 NC PWRGD ILIM_EN 4 1400mA 750mA 300mA INPUT CURRENT LIMIT + PWRGD 14V – VPORTN 6 VNEG VNEG VPORTN 7 VNEG BOLD LINE INDICATES HIGH CURRENT PATH VCC CLAMPS 20V 0.7 + – 1.237V REFERENCE (VFB) FB 1.
LTC4268-1 Applications Information Overview OPERATION Power over Ethernet (PoE) continues to gain popularity as an increasing number of products are taking advantage of having DC power and high speed data available from a single RJ45 connector. As PoE is becoming established in the marketplace, Powered Device (PD) equipment vendors are running into the 12.95W power limit established by the IEEE 802.3af standard.
LTC4268-1 Applications Information DETECTION V1 –10 VPORTN (V) TIME DETECTION V2 CLASSIFICATION –20 UVLO TURN-ON –30 –40 UVLO TURN-OFF –50 TIME τ = RLOAD C1 –10 UVLO OFF VIN (V) –20 UVLO ON UVLO OFF –30 –40 dV =ILIMIT_LOW dt C1 –50 The PD must be able to handle power received in either polarity. For this reason, it is common to install diode bridges between the RJ45 connector and the LTC4268-1 (Figure 3).
LTC4268-1 Applications Information tie SHDN to VPORTP. Alternately, the SHDN pin can be driven high with respect to VPORTN. When SHDN is high, all functions are disabled. For normal operation tie SHDN to VPORTN. Table 1. LTC4268-1 Operational Mode as a Function of VPORT Voltage VPORT MODE OF OPERATION 0V to –1.4V Inactive –1.5V to –10.1V 25k Signature Resistor Detection –10.3V to –12.4V Classification Load Current Ramps Up from 0% to 100% –12.
LTC4268-1 Applications Information classification for use in closed systems and is not defined or supported by the IEEE 802.3af. With the extended classification range available in the LTC4268-1, it is possible for system designers to define multiple classes using load currents between 40mA and 75mA. During classification, the PSE presents a fixed voltage between –15.5V and –20.5V to the PD (Figure 5).
LTC4268-1 Applications Information UNDERVOLTAGE LOCKOUT INPUT CURRENT LIMIT The IEEE 802.3af specification dictates a maximum turn‑on voltage of 42V and a minimum turn-off voltage of 30V for the PD. In addition, the PD must maintain large on-off hysteresis to prevent current-resistance (I-R) drops in the wiring between the PSE and the PD from causing start-up oscillation.
LTC4268-1 Applications Information During the inrush event as C1 is being charged, a large amount of power is dissipated in the MOSFET. The LTC4268-1 is designed to accept this load and is thermally protected to avoid damage to the onboard power MOSFET. If a thermal overload does occur, the power MOSFET turns off, allowing the die to cool. Once the die has returned to a safe temperature, the LTC4268-1 automatically switches to ILIMIT_LOW, and load capacitor C1 charging resumes.
LTC4268-1 Applications Information consume a lot of power, it is important to delay activation of the DC/DC converter with the power good signal. If the converter is not disabled during the current-limited turn-on sequence, the DC/DC converter will rob current intended for charging up the load capacitor and create a slow rising input, possibly causing the LTC4268-1 to go into thermal shutdown. The active high PWRGD pin features an internal, open‑collector output referenced to VNEG.
LTC4268-1 Applications Information EXTERNAL INTERFACE AND COMPONENT SELECTION Table 4. Power over Ethernet Transformer Vendors VPORT Transformer Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer (Figure 9). For powered devices, the isolation transformer must include a center tap on the media (cable) side. Proper termination is required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions.
LTC4268-1 Applications Information PD is required to accept power in either polarity on both the data and spare inputs; therefore it is common to install diode bridges on both inputs in order to accommodate the different wiring configurations. Figure 9 demonstrates an implementation of the diode bridges to minimize heating. The IEEE 802.3af specification also mandates that the leakage back through the unused bridge be less than 28µA when the PD is powered with 57V.
LTC4268-1 Applications Information OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4268-1 RJ45 1 2 3 6 TX+ T1 ~ TX– RX+ TO PHY BR1 ~ RX– D3 SMAJ58A TVS + + C14 0.
LTC4268-1 Applications Information to the PSE power. The PD will draw power from the PSE while the adapter will remain unused. This configuration is acceptable in a typical PoE system. However, if the adapter voltage is higher than the PSE voltage, the PD will draw power from the adapter. In this situation, it is necessary to address the issue of power cycling that may occur if a PSE is present. The PSE will detect the PD and apply power.
LTC4268-1 Applications Information Power Good Interface The LTC4268-1 provides complimentary power good signals to simplify the DC/DC converter interface. Using the power good signal to delay converter operation until the load capacitor is fully charged is recommended as this will help ensure trouble free start-up. The active high PWRGD pin is controlled by an open collector transistor referenced to VNEG while the active low PWRGD pin is controlled by a high voltage, open-drain MOSFET referenced to VPORTN.
LTC4268-1 Applications Information MAINTAIN POWER SIGNATURE In an IEEE 802.3af system, the PSE uses the maintain power signature (MPS) to determine if a PD continues to require power. The MPS requires the PD to periodically draw at least 10mA and also have an AC impedance less than 26.25k in parallel with 0.05µF. If either the DC current is less than 10mA or the AC impedance is above 26.25k, the PSE may disconnect power.
LTC4268-1 Applications Information The flyback voltage is scaled by an external resistive divider R1/R2 and presented at the FB pin. The feedback amplifier compares the voltage to the internal bandgap reference. The feedback amp is actually a transconductance amplifier whose output is connected to VCMP only during a period in the flyback time. An external capacitor on the VCMP pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point.
LTC4268-1 Applications Information side MOSFET drain node but, more importantly, is due to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to output voltage. Some time is also required for internal settling of the feedback amplifier circuitry. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.
LTC4268-1 Applications Information lowpass filtered by the internal 50k resistor RCMPF and the external capacitor on CCMP. This voltage is impressed across the external RCMP resistor by op amp A1 and transistor Q3 producing a current at the collector of Q3 that is subtracted from the FB node. This effectively increases the voltage required at the top of the R1/R2 feedback divider to achieve equilibrium.
LTC4268-1 Applications Information In general, better performance is obtained with a lower turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. Turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance.
LTC4268-1 Applications Information behavior—is the most apt to be bistable. Capacitive loads that exhibit I = V2/R behavior are less susceptible. Secondary Leakage Inductance Leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the flyback pulse. This increases the output voltage target by a similar percentage. Note that unlike leakage spike behavior; this phenomenon is independent of load.
LTC4268-1 Applications Information Transformer Core Selection Once LP is known, the type of transformer is selected. High efficiency converters use ferrite cores to minimize core loss. Actual core loss is independent of core size for a fixed inductance, but decreases as inductance increases. Since increased inductance is accomplished through more turns of wire, copper losses increase. Thus transformer design balances core and copper losses.
LTC4268-1 Applications Information Size RSENSE using worst-case conditions, minimum LP, VSENSE and maximum VIN. Continuing the example, let us assume that our worst-case conditions yield an IPK of 40% above nominal so IPK = 2.3A. If there is a 10% tolerance on RSENSE and minimum VSENSE = 88mV, then RSENSE • 110% = 88mV/2.3A and nominal RSENSE = 35mW. Round to the nearest available lower value, 33mW.
LTC4268-1 Applications Information Setting Frequency Selecting Timing Resistors The switching frequency of the LTC4268-1 is set by an external capacitor connected between the OSC pin and ground. Recommended values are between 200pF and 33pF, yielding switching frequencies between 50kHz and 250kHz. Figure 15shows the nominal relationship between external capacitance and switching frequency.
LTC4268-1 Applications Information minimum on time along with synchronous rectification sets the switch over to forced continuous mode operation. The tON(MIN) resistor is set with the following equation R tON(MIN) (kW ) = tON(MIN) (ns ) − 104 1.063 Keep RtON(MIN) greater than 70k. A good starting value is 160k. Enable Delay Time (ENDLY) Enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback amplifier.
LTC4268-1 Applications Information Converter Start-Up If CTR is undersized, VCC reaches the VCC turn-off threshold before stabilization and the LTC4268-1 turns off. The VCC node then begins to charge back up via RTR to the turn‑on threshold, where the part again turns on. Depending upon the circuit, this may result in either several on-off cycles before proper operation is reached, or permanent relaxation oscillation at the VCC node.
LTC4268-1 Applications Information The LTC4268-1 has an internal clamp on VCC of approximately 20V. This provides some protection for the part in the event that the switcher is off (UVLO low) and the VCC node is pulled high. If RTR is sized correctly the part should never attain this clamp voltage. Slope Compensation The LTC4268-1 incorporates current slope compensation. Slope compensation is required to ensure current loop stability when the DC is greater than 50%.
LTC4268-1 Applications Information max 100mV rating because of the minimum switch on time blanking. If the voltage on VSENSE exceeds 205mV after the minimum turn-on time, the SFST capacitor is discharged, causing the discharge of the VCMP capacitor. This then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. Short-Circuit Conditions Loss of current limit is possible under certain conditions such as an output short circuit.
LTC4268-1 Applications Information Power MOSFET Selection The power MOSFETs are selected primarily on the criteria of “on” resistance RDS(ON), input capacitance, drain-to‑source breakdown voltage (BVDSS), maximum gate voltage (VGS) and maximum drain current (ID(MAX)). Choose the primary side MOSFET RDS(ON) at the nominal gate drive voltage (7.5V). The secondary side MOSFET gate drive voltage depends on the gate drive method.
LTC4268-1 Applications Information With CMILLER determined, calculate the primary-side power MOSFET power dissipation: PD(PRI) =IRMS(PRI)2 • RDS(ON) (1+ d ) + VIN(MAX) • PIN(MAX) DCMIN • RDR • CMILLER •f VGATE(MAX) − VTH OSC where: RDR is the gate driver resistance (≈10W) VTH is the MOSFET gate threshold voltage fOSC is the operating frequency VGATE(MAX) = 7.5V for this part (1 + d) is generally given for a MOSFET in the form of a normalized RDS(ON)vs temperature curve.
LTC4268-1 Applications Information The output capacitor should have an RMS current rating greater than: IRMS(SEC) =IOUT DCMAX 1− DCMAX ESRCOUT ≤ 1% • Continuing the example: IRMS(SEC) = 5.3A to the total ripple voltage, the ESR of the output capacitor is determined by: VOUT • (1− DCMAX ) IOUT The other 1% is due to the bulk C component, so use: 49.4% = 5.24A 1− 49.4% COUT ≥ This is calculated for each output in a multiple winding application.
LTC4268-1 Applications Information Most capacitor ripple current ratings are based on 2000 hour life. This makes it advisable to derate the capacitor or to choose a capacitor rated at a higher temperature than required. there will be any user accessible connection to the PD, then an isolated DC/DC converter is necessary to meet the isolation requirements. If user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the PD in an insulated housing.
LTC4268-1 Applications Information the MOSFET node voltages with an oscilloscope. If it is breaking down either choose a higher voltage device, add a snubber or specify an avalanche-rated MOSFET. In order to minimize switching noise and improve output load regulation, connect the GND pin of the LTC4268-1 directly to the ground terminal of the VCC decoupling capacitor, the bottom terminal of the current sense resistor and the ground terminal of the input capacitor, using a ground plane with multiple vias.
RJ45 8 7 5 4 6 3 2 1 J1 XFMR SPARE– SPARE+ R5 75Ω 8 10 9 7 11 RX– 3 6 14 2 RX+ 15 TX– TX+ T3 ETH1–230LD 16 1 –54V IN FROM HIGH POWER PSE C14 0.01µF 200V TO PHY R4 75Ω C16 0.01µF 200V R7 75Ω R6 75Ω C15 0.01µF 200V J3 D6 24V 30W AUX POWER IN C13 0.01µF 200V D7 C44 0.001µF D2 2kV D3 D9 D8 D5 D4 0.1µF 100V B2100X8 VPORTP R18 100k R14 4.7k R21 20k Q5 FMMT723 D1 SMAJ58A 10Ω C1A 12µF 100V PWRGD 100k PWRGD C1B 2.
LTC4268-1 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DKD Package 32-Lead Plastic DFN (7mm × 4mm) (Reference LTC DWG # 05-08-1734 Rev A) 0.70 ±0.05 4.50 ±0.05 6.43 ±0.05 2.65 ±0.05 3.10 ±0.05 PACKAGE OUTLINE 0.20 ±0.05 0.40 BSC 6.00 REF RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ±0.10 17 R = 0.115 TYP 32 R = 0.05 TYP 0.40 ±0.10 6.43 ±0.10 4.00 ±0.10 2.65 ±0.
LTC4268-1 Revision History (Revision history begins at Rev C) REV DATE DESCRIPTION C 08/12 Simplified Overview section, including removal of Figure 1A and 1B which caused renumbering of all figures in data sheet PAGE NUMBER Changed maximum power levels for class 0 and class 3 to 13.
LTC4268-1 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4257-1 IEEE 802.3af PD Interface Controller 100V 400mA Internal Switch, Programmable Classification Dual Current Limit LTC4258 Quad IEEE 802.3af Power over Ethernet Controller DC Disconnect Only, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control LTC4259A-1 Quad IEEE 802.
