Datasheet

LTC4267-1
27
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applicaTions inForMaTion
P
VCC
below the P
VCC
turn-off threshold. Employing the
second example has the added advantage of adding delay
to the switching regulator start-up beyond the time the
power good signal becomes active. The second example
ensures additional timing margin at start-up without the
need for added delay components. In applications where it
is not desirable to utilize the power good signal, sufficient
timing margin can be achieved with R
START
and C
PVCC
.
R
START
and C
PVCC
should be set to a delay of two to three
times longer than the duration needed to charge up C1.
Layout Considerations for the LTC4267-1
The most critical layout considerations for the LTC4267-1
are the placement of the supporting external components
associated with the switching regulator. Efficiency, stabil-
ity, and load transient response can deteriorate without
good layout practices around critical components.
For the LTC4267-1 switching regulator, the current loop
through C1, T1 primary, Q1, and R
SENSE
must be given
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should
be used between these components. If vias are
n
ecessary to complete the connectivity of this loop, placing
multiple vias lined perpendicular to the flow of current is
essential for minimizing parasitic resistance and reducing
current density. Since the switching frequency and the
power levels are substantial, shielding and high frequency
layout techniques should be employed. A low current,
low impedance alternate connection should be employed
between the PGND pins of the LTC4267-1 and the PGND
side of R
SENSE
, away from the high current loop. This
Kelvin sensing will ensure an accurate representation of
the sense voltage is measured by the LTC4267-1.
The placement of the feedback resistors R1 and R2 as
well as the compensation capacitor C
C
is very important
in the accuracy of the output voltage, the stability of the
main control loop, and the load transient response. In
an isolated design application, R1, R2, and C
C
should be
placed as close as possible to the error amplifier’s input
with minimum trace lengths and minimum capacitance. In
a nonisolated application, R1, and R2 should be placed as
close as possible to the V
FB
pin of the LTC4267-1 and C
C
should be placed close to the I
TH
/RUN pin of the LTC4267-1.
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure suc-
cessful operation of the LTC4267-1 in a PD.
Place C14 (Figure 9) as close as physically possible to the
LTC4267-1 across V
PORTP
and V
PORTN
. Place the series
10Ω resistor close to C14. Excessive parasitic capacitance
on the R
CLASS
pin should be avoided. The SIGDISA pin is
adjacent to the V
PORTP
pin and any coupling, whether resis-
tive or capacitive may inadvertently disable the signature
resistance. To ensure consistent behavior, the SIGDISA
pin should be electrically connected and not left floating.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.