Datasheet

LTC4267-1
10
42671fa
For more information www.linear.com/4267-1
applicaTions inForMaTion
Using an LTC4267-1 for the power and signature inter-
face functions of a PD provides several advantages. The
LTC4267-1 current limit circuit includes an onboard 100V
power MOSFET. This low leakage MOSFET is specified to
avoid corrupting the 25k signature resistor while also sav-
ing board space and cost. In addition, the inrush current
limit requirement of the IEEE 802.3af standard can cause
large transient power dissipation in the PD. The LTC4267-1
is designed to allow multiple turn-on sequences without
overheating the miniature 16-lead package. In the event of
excessive power cycling, the LTC4267-1 provides thermal
overload protection to keep the onboard power MOSFET
within its safe operating area.
OPERATION
The LTC4267-1 PD interface has several modes of opera-
tion depending on the applied input voltage as shown in
Figure 1 and summarized in Table 1. These modes satisfy
the requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the V
PORTN
pin and must
be negative relative to the V
PORTP
pin. Voltages in the data
sheet for the PD interface portion of the LTC4267-1 are
with respect to V
PORTP
while the voltages for the switch-
ing regulator are referenced to PGND. It is assumed that
PGND
is tied to P
OUT
. Note the use of different ground
symbols throughout the data sheet.
Table 1. LTC4267-1 Operational Mode
as a Function of Input Voltage
INPUT VOLTAGE
(V
PORTN
with RESPECT to V
PORTP
) LTC4267-1 MODE OF OPERATION
0V to –1.4V Inactive
–1.5V to –9.5V** 25k Signature Resistor Detection
–9.8V to –12.4V Classification Load Current Ramps up
from 0% to 100%
–12.5V to UVLO* Classification Load Current Active
UVLO* to –57V Power Applied to Switching Regulator
* V
PORTN
UVLO includes hysteresis.
Rising input threshold ≅ –36.0V
Falling input threshold ≅ –30.5V
** Measured at LTC4267-1 pin. The LTC4267-1 meets the IEEE 802.3af
10V minimum when operating with the required diode bridges.
Figure 1. Output Voltage, PWRGD and PD
Current as a Function of Input Voltage
DETECTION V1
CLASSIFICATION
UVLO
TURN-ON
UVLO
OFF
POWER
BAD
UVLO
OFF
UVLO
ON
UVLO
TURN-OFF
τ = R
LOAD
C1
PWRGD TRACKS
V
PORTN
DETECTION V2
–10
TIME
–20
–30
V
PORTN
(V)
–40
–50
–10
TIME
–20
–30
P
OUT
(V)
–40
–50
–10
TIME
–20
–30
PWRGD (V)
–40
–50
I
CLASS
PD CURRENT
I
LIM_LO
dV
dt
I
LIM_LO
C1
=
POWER
BAD
POWER
GOOD
DETECTION I
1
CLASSIFICATION
I
CLASS
DETECTION I
2
LOAD, I
LOAD
(UP TO I
LIM_HI
)
CURRENT
LIMIT, I
LIM_LO
42671 F01
I
CLASS
DEPENDENT ON R
CLASS
SELECTION
I
LIM_LO
= 140mA (NOMINAL), I
LIM_HI
= 375mA (NOMINAL)
I
1
=
V1 – 2 DIODE DROPS
25kΩ
I
LOAD
= (UP TO I
LIM_HI
)
V
OUT
R
LOAD
I
2
=
V2 – 2 DIODE DROPS
25kΩ
V
PORTP
PSE
I
IN
LTC4267-1
R9
R
CLASS
R
LOAD
V
OUT
C1
R
CLASS
PWRGD
P
OUT
PGND
V
PORTN
V
IN
TIME
VOLTAGES WITH RESPECT TO V
PORTP