Datasheet
LTC4264
8
4264f
APPLICATIONS INFORMATION
4264 F02
SMAJ58A
0.1µF
Tx1
Rx1
Rx1
Tx1
SMAJ58A
V
EE
SENSE GATE OUT
V
DD
AUTO
CMPD3003
10k
1k
0.1
µF
0.25Ω
IRLR3410
S1B
1/4
LTC4259A
DGND
BYP AGND
DETECT
3.3V
–54V
1
RJ45
RJ45
CAT5
2
1
2
3
6
3
6
PSE
PD
R
CLASS
V
IN
PWRGD
V
OUT
LTC4264
GND
DF1501S
DF1501S
DC/DC
CONVERTER
5µF
MIN
+
+
+
–
–
–
V
OUT
GND
0.47µF
SMAJ58A
0.1µF
Tx2
Rx2
Rx2
Tx2
V
EE
SENSE GATE OUT
CMPD3003
10k
1k
0.25Ω
IRLR3410
S1B
1/4
LTC4259A
DETECT
–54V
4
5
4
5
7
8
7
8
GND
0.47µF
0.1µF
SMAJ58A
R
CLASS
V
IN
PWRGD
V
OUT
LTC4264
GND
DC/DC
CONVERTER
5µF
MIN
0.1µF
AGND
Figure 2. 4-Pair High Power PoE Gigabit Ethernet System Diagram
The LTC4264 is specifi cally designed to implement the
front end of a high power PD for power-hungry PoE ap-
plications that must operate beyond the power limits of
IEEE 802.3af. LTC4264 uses a precision, dual current limit
that keeps inrush below IEEE 803.2af levels to ensure
interoperability with any PSE. After inrush is complete,
the LTC4264 input current limit switches to the I
LIMIT_HIGH
level, using an onboard, 750mA power MOSFET. This al-
lows a PD (supplied by a custom PSE) to deliver power
above the IEEE 802.3af 12.95W maximum, sending up
to 35W to the PD load. The LTC4264 uses established
IEEE 802.3af detection and classifi cation methods to
maintain compliance and includes an extended program-
mable Class 5 range for use in custom PoE applications.
The LTC4264 features both active-high and active-low
power good signaling for simplifi ed interface to any DC/DC
converter. The SHDN pin on the LTC4264 can be used to
provide a seamless interface for external wall adapter or
other auxiliary power options. The I
LIM_EN
pin provides the
option to remove the high current limit, I
LIMIT_HIGH
. The
LTC4264 includes an onboard signature resistor, precision
UVLO, thermal overload protection and is available in a
thermally-enhanced 12-lead 4mm × 3mm DFN package
for superior high current performance.
OPERATION
The LTC4264 high power PD interface controller has sev-
eral modes of operation depending on the applied input
voltage as shown in Figure 3 and summarized in Table 1.
These various modes satisfy the requirements defi ned
in the IEEE 802.3af specifi cation. The input voltage is
applied to the V
IN
pin with reference to the GND pin and
is always negative.
Table 1. LTC4264 Operational Mode as a Function
of Input Voltage
INPUT VOLTAGE LTC4264 MODE OF OPERATION
0V to –1.4V Inactive
–1.5V to –10.1V 25k Signature Resistor Detection
–10.3V to –12.4V Classifi cation Load Current Ramps Up from 0% to
100%
–12.5V to UVLO* Classifi cation Load Current Active
UVLO* to –57V Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold ≅ –38.9V
Falling input threshold ≅ –30.6V