Datasheet

LTC4253B
9
4253bf
RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-
chronous TTL compatible input. RESET going high will pull
GATE, SS, TIMER, SQTIMER low
and the PWRGD outputs
high. The RESET pulse must be wide enough to discharge
any voltage on the TIMER pin below V
TMRL
. After the reset
of a latched fault, the chip waits for the interlock conditions
before recovering as described in Interlock Conditions in
the Operation section.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over di/dt.
A 20X attenuated version of the SS pin voltage is presented
to the current limit amplifier. This attenuated voltage limits
the MOSFET’s drain current through the sense resistor
during the soft-start current limiting. At the beginning
of the start-up cycle, the SS capacitor (C
SS
) is ramped
by a 22µA current source. The GATE pin is held low until
SS exceeds 20 • V
OS
= 0.2V. SS is internally shunted by
a 100k R
SS
which limits the SS pin voltage to 2.2V. This
corresponds to an analog current limit SENSE voltage of
100mV. If the SS capacitor is omitted, the SS pin ramps
up
in about 250µs. The SS pin is pulled low under any of
the following conditions: UVLO at V
IN
, UV, OV, during the
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high.
SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin.
Load current is monitored by a sense resistor R
S
connected
between
SENSE and V
EE
, and controlled in three steps. If
SENSE exceeds V
CB
(50mV), the circuit breaker compara-
tor activates a (200µA+8•I
DRN
) TIMER pull-up current.
If SENSE exceeds V
ACL
, the analog current-limit amplifier
pulls GATE down to regulate the MOSFET current at V
ACL
/
R
S
. In the event of a catastrophic short-circuit, SENSE may
overshoot V
ACL
. If SENSE reaches V
FCL
(200mV), the fast
current-limit comparator pulls GATE low with a strong
pull-down. To disable the circuit breaker and current limit
functions, connect SENSE
to V
EE
.
V
EE
(Pin 8): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
GATE (Pin 9): N-channel MOSFET Gate Drive Output. This
pin is pulled high by a 50µA current source. GATE is pulled
low by invalid conditions at V
IN
(UVLO), UV, OV, during the
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high. GATE is actively servoed to control
the fault current as measured at SENSE. Compensation
capacitor, C
C
, at GATE stabilizes this loop. A comparator
monitors GATE to ensure that it is low before allowing an
initial timing cycle, then the GATE ramps up after an over-
voltage event or restart after a current limit fault. During
GATE start-up, a second comparator detects GATE within
2.8V of V
IN
before PWRGD1 can be set and power good
sequencing starts.
DRAIN (Pin 10): Drain Sense Input. Connecting an exter-
nal resistor, R
D
between this pin and the MOSFET’s drain
(V
OUT
) allows voltage sensing below 6.15V and current
feedback to TIMER. A comparator detects if DRAIN is below
2.39V and together with the GATE high comparator, sets
the PWRGD1 flag. If V
OUT
is above V
DRNCL
, the DRAIN
pin is clamped at approximately V
DRNCL
. R
D
current is
internally multiplied by 8 and added to TIMER’s 200µA
during a circuit breaker fault cycle. This reduces the fault
time and MOSFET heating.
OV (Pin 11): Overvoltage Input. For the LTC4253B, the
threshold
at the OV pin is set at 6.15V with 0.3V hysteresis.
If
OV > 6.15V, GATE pulls low. When OV returns below
5.85V, GATE start-up begins without an initial timing cycle.
If OV occurs in the middle of an initial timing cycle, the
initial timing cycle is restarted after OV goes away. OV
does not reset the latched fault or PWRGD1 flag. The
internal UVLO at V
IN
always overrides OV. A 1nF to 10nF
capacitor at OV prevents transients and switching noise
from affecting the OV thresholds and prevents glitches
at the GATE.
pin FuncTions