Datasheet

LTC4253B
24
4253bf
applicaTions inForMaTion
addition, the internal logic checks for OV < V
OVHI
, RESET
< 0.8V, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 • V
OS
and
TIMER<V
TMRL
. When all conditions are met, initial timing
starts and the TIMER capacitor is charged by a 5µA current
source pull-up. At time point 3, TIMER reaches the V
TMRH
threshold and the initial timing cycle terminates. The TIMER
capacitor is quickly discharged. At time point4, the V
TMRL
threshold is reached and the conditions of GATE<V
GATEL
,
SENSE<V
CB
and SS<20 • V
OS
must be satisfied before
the GATE start-up cycle begins. SS ramps up as dictated
by R
SS
• C
SS
; GATE is held low by the analog current
limit amplifier until SS crosses 20 • V
OS
. Upon releasing
GATE, 50µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed and the SENSE voltage is regulated at V
ACL
(t)
and soft-start limits the slew rate of the load current. If the
SENSE
voltage (V
SENSE
– V
EE
) reaches the V
CB
threshold
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, C
T
is charged by a (200µA+8•I
DRN
)
current pull-up. As the load capacitor nears full charge,
load current begins to decline. At point8, the load cur-
rent falls and the SENSE voltage drops below V
ACL
(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V
CB
and the fault TIMER ends, followed by a 5µA
discharge current source (cool-off). When GATE ramps
past V
GATEH
threshold at time point A, PWRGD1 pulls low,
starting off the PWRGD sequence. PWRGD2 pulls low at
time point C when EN2 is high and PWRGD1 is low for
more than one t
SQT
. PWRGD3 pulls low at time point D
when EN2 and EN3 is high and PWRGD2 is low for more
than one t
SQT
. At time point B, GATE reaches its maximum
voltage as determined by V
IN
.
Undervoltage Timing
In Figure 9 when the UV pin drops below V
UVLO
at time
point 1, the LTC4253B shuts down with TIMER, SS and
GATE pulled low. If
current has been flowing, the SENSE
pin
voltage decreases to zero as GATE collapses. When
UV recovers and clears V
UVHI
at time point 2, an initial
time cycle begins followed by a start-up cycle.
V
IN
Undervoltage Lockout Timing
V
IN
undervoltage lockout comparator, UVLO has a similar
timing behavior as the UV pin timing except it looks at
V
IN
< (V
LKO
–V
LKH
) to shut down and V
IN
> V
LKO
to start.
In an undervoltage lockout condition, both UV and OV
comparators are held off. When V
IN
exits undervoltage
lockout, the UV and OV comparators are enabled.
Overvoltage Timing
During normal operation, if the OV pin exceeds V
OVHI
as
shown at time point 1 of Figure 10, the TIMER and PWRGD
status are unaffected; SS and GATE pull down; load discon-
nects. At time point 2, OV recovers and drops below the
V
OVLO
threshold; GATE start-up begins. If the overvoltage
glitch is long enough to deplete the load capacitor, time
points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 11a, the TIMER capacitor charges at 200µA if
the SENSE pin exceeds V
CB
but V
DRN
is less than 5V. If
the SENSE pin returns below V
CB
before TIMER reaches
the V
TMRH
threshold, TIMER is discharged by 5µA. In
Figure 11b, when TIMER exceeds V
TMRH
, GATE pulls
down immediately and the chip shuts down. In Figure11c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach V
TMRH
followed by GATE pull down and
the chip shuts down. During chip shutdown, the LTC4253B
latches TIMER high with a 5µA pull-up current source.