Datasheet

LTC4253B
17
4253bf
applicaTions inForMaTion
POWER GOOD SEQUENCING
After the initial TIMER cycle, GATE ramps up to turn on
the external MOSFET which in turn pulls DRAIN low.
When GATE is within 2.8V of V
IN
and DRAIN is lower than
V
DRNL
, the power good sequence starts with PWRGD1
pulling active low. This starts off a 5µA pull-up on the
SQTIMER pin which ramps up until it reaches the 4V
threshold then pulls low. When the SQTIMER pin floats,
this delay t
SQT
is about 300µs. Connecting an external
capacitor C
SQ
from SQTIMER to V
EE
modifies the delay to:
t
SQT
=
4V • C
SQ
5µA
(5)
PWRGD2 asserts when EN2 goes high and PWRGD1 has
asserted for more than one t
SQT
. When PWRGD2 suc-
cessfully pulls low, SQTIMER ramps up on another delay
cycle. PWRGD3 asserts when EN2 and EN3 go high and
PWRGD2 has asserted for more than one t
SQT
.
All three PWRGD signals are reset in UVLO, in UV condi-
tion, if RESET is high or when C
T
charges up to 4V. In
addition, PWRGD2 is reset by EN2 going low. PWRGD3 is
reset by EN2 or EN3 going low. An overvoltage condition
has no effect on the PWRGD flags. A 50µA current pulls
each PWRGD pin high when reset. As power modules
signal common are different from PWRGD, optoisolation
is recommended. These three pins can sink an optodiode
current. Figure 16 shows an NPN configuration for the
PWRGD interface. A limiting base resistor should be used
for each NPN and the module enable input should have
protection from negative bias current.
SOFT-START
Soft-start is effective in limiting the inrush current during
GATE start-up. Unduly long soft-start intervals can exceed
the MOSFET’s SOA duration if powering-up into an active
load. When the SS pin
floats, an internal current source
ramps
SS from 0V to 2.2V in about 300µs. Connecting an
external capacitor, C
SS
, from SS to ground modifies the
ramp to approximate an RC response of:
V
SS
(t) ≈ V
SS
1− e
– t
R
SS
C
SS








(6)
An internal resistor divider (95k/5k) scales V
SS
(t) down
by 20 times to give the analog current limit threshold:
V
ACL
(t)=
V
SS
(t)
20
– V
OS
(7)
This allows the inrush current to be limited to V
ACL
(t)/R
S
.
The offset voltage, V
OS
(10mV), ensures C
SS
is sufficiently
discharged and the ACL amplifier is in current limit mode
before GATE start-up. SS is discharged low during UVLO
at V
IN
, UV, OV, during the initial timing cycle, a latched
circuit breaker fault or the RESET pin going high.
GATE
GATE is pulled low to V
EE
under any of the following condi-
tions: in UVLO, when RESET pulls high, in an undervoltage
condition, in an overvoltage condition, during the initial
timing cycle or a latched circuit breaker fault. When GATE
turns on, a 50µA current source charges the MOSFET gate
and any associated external capacitance. V
IN
limits the
gate drive to no more than 14.5V.
Gate-drain capacitance (C
GD
) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
IN
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating C
GD
. Instead, a smaller value (≥10nF)
capacitor C
C
is adequate. C
C
also provides compensation
for the analog current limit loop.
GATE has two comparators: the GATE low comparator looks
for <0.5V threshold prior to initial timing; the GATE high
comparator looks for <2.8V relative to V
IN
and, together
with DRAIN low comparator, sets PWRGD1 output during
GATE start-up.