Datasheet

LTC4253B
16
4253bf
applicaTions inForMaTion
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor C
T
is used at
TIMER to provide timing for the LTC4253B. Four different
charging and discharging modes are available at TIMER:
1. 5µA slow charge; initial timing delay.
2. (200µA+8•I
DRN
) fast charge; circuit breaker delay.
3. 5µA slow discharge; circuit breaker “cool-off.”
4. Low impedance switch; resets the TIMER capacitor after
an initial timing delay, in UVLO, in UV and in OV during
initial timing and when RESET is high.
For initial timing delay, the 5µA pull-up is used. The
low impedance switch is turned off and the 5µA current
source is enabled when the interlock conditions are met.
C
T
charges to 4V in a time period given by:
t =
4V • C
T
5µA
(2)
When C
T
reaches V
TMRH
( 4V), the low impedance switch
turns on and discharges C
T
. A GATE start-up cycle begins
and both SS and GATE outputs are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV drop across R
S
,
the TIMER pin charges C
T
with (200µA+8•I
DRN
). If C
T
charges to 4V, the GATE pin pulls low and the LTC4253B
latches off. The LTC4253B remains latched off until the
RESET pin is momentarily pulsed high, the UV pin is
momentarily pulsed low, the TIMER pin is momentarily
discharged low by an external switch or V
IN
dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
t =
4V • C
T
200µA + 8 • I
DRN
(3)
If V
OUT
< 5V, an internal PMOS isolates DRAIN pin leakage
current and this makes I
DRN
= 0 in Equation (3). If V
OUT
is
above V
DRNCL
during the circuit breaker fault period, the
charging of C
T
is accelerated by 8 • I
DRN
of Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE but, if their duration is sufficiently short, TIMER
will not reach 4V and the LTC4253B will not shut the
external MOSFET off. To handle this situation, the TIMER
discharges C
T
slowly with a 5µA pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with V
OUT
< 5V and an aggregate duty cycle
of more than 2.5% will eventually trip the circuit breaker
and shut down the LTC4253B. Figure 3 shows the circuit
breaker response time in seconds normalized to 1µF. The
asymmetric charging and discharging of C
T
is a fair gauge
of MOSFET heating.
The normalized circuit response time is estimated by:
t
C
T
(µF)
=
4
205 + 8 •I
DRN
( )
• D− 5




for D> 2.5%
(4)
FAULT DUTY CYCLE, D (%)
20 40 60 800
NORMALIZED RESPONSE TIME (s/µF)
10
1
0.1
0.01
100
4253b F03
t
C
T
(µF)
4
(205 + 8 • I
DRN
) • D – 5
=
I
DRN
= 0µA
Figure 3. Circuit Breaker Response Time