Datasheet

LTC4253B
15
4253bf
applicaTions inForMaTion
pulse. To protect V
IN
against damage from higher am-
plitude spikes, clamp V
IN
to V
EE
with a 13V Zener diode.
Star connect V
EE
and all V
EE
-referred components to the
sense resistor Kelvin terminal as illustrated in Figure 2,
keeping trace lengths between V
IN
, C
IN
, D
IN
and V
EE
as
short as possible.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
A hysteretic comparator, UVLO, monitors V
IN
for undervolt-
age. The thresholds are defined by V
LKO
and its hysteresis
V
LKH
. When V
IN
rises above V
LKO
, the chip is enabled;
below (V
LKO
– V
LKH
), it is disabled and GATE is pulled low.
The UVLO function at V
IN
should not be confused with the
UV and OV pins. These are completely separate functions.
UV/OV COMPARATORS
A UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (V
UVHI
) = 3.225V
UV high-to-low (V
UVLO
) = 2.925V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
OV low-to-high (V
OVHI
) = 6.150V
OV high-to-low (V
OVLO
) = 5.850V
The UV and OV trip point ratio is designed to match the
standard telecom operating
range of 43
V to 82V when
connected together as in the Typical Application. A resistive
divider is used to scale the supply voltage. Using 402k and
32.4k gives a typical operating range of 43.2V to 82.5V.
The undervoltage shutdown and overvoltage recovery
thresholds are then 39.2V and 78.4V. 1% divider resistors
are recommended to preserve threshold accuracy.
The resistive divider values shown set a standing current
of slightly more than 100µA and define an impedance at
UV/OV of 30kΩ. In most applications, 30kΩ impedance
coupled with 300mV UV hysteresis make the LTC4253B
insensitive to noise. If more noise immunity is desired,
add a 1nF to 10nF filter capacitor from UV/OV to V
EE
.
The separate UV and OV pins can be used for wider op-
erating range such as 35.6V to 76.3V range as shown in
Figure 2. Other combinations are possible with different
resistors arrangement.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in the
UV comparator immediately shuts down the
LTC4253B,
pulls
the MOSFET gate low and resets the three latched
PWRGD signals high.
An overvoltage condition is detected by the OV compara-
tor and pulls GATE low, thereby shutting down the load,
but it will not reset the circuit breaker TIMER and PWRGD
flags. Returning from the overvoltage condition will
restart the GATE pin if all the interlock conditions except
TIMER are met. Only during the initial timing cycle does
OV condition have an effect of resetting TIMER.
DRAIN
Connecting an external resistor, R
D
, to this dual function
DRAIN pin allows V
OUT
(MOSFET drain-source voltage
drop) sensing without it being damaged by large volt-
age transients. Below 5V, negligible pin leakage allows
a DRAIN low comparator to detect V
OUT
less than 2.39V
(V
DRNL
). This, together with the GATE low comparator,
sets the PWRGD flag.
When V
OUT
> V
DRNCL
, the DRAIN pin is clamped at V
DRNCL
and the current flowing in R
D
is given by:
I
DRN
≈
V
OUT
−
V
DRNCL
R
D
(1)
This current is scaled up 8 times during a circuit breaker
fault before being added to the nominal 200µA. This ac-
celerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds V
DRNCL
and effectively
shortens the MOSFET heating duration.