Datasheet

LTC4253B
14
4253bf
applicaTions inForMaTion
operaTion
Higher overloads are handled by an analog current limit
loop. If the drop across R
S
reaches V
ACL
, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of V
ACL
/R
S
. In current limit mode,
V
OUT
(MOSFET drain-source voltage drop) typically rises
and this increases MOSFET heating. If V
OUT
> V
DRNCL
,
connecting an external resistor, R
D
between V
OUT
and
DRAIN allows the fault timing cycle to be shortened by
accelerating the charging of the TIMER capacitor. The
TIMER pull-up current is increased by 8 • I
DRN
. Note that
because SENSE > 50mV, TIMER charges C
T
during this
time, and the LTC4253B eventually shuts down.
Low impedance failures on the load side of the LTC4253B,
coupled with 48V or more driving potential, can produce
current slew rates well in excess of 50A/µs. Under these
conditions, overshoot is inevitable. A fast SENSE com-
parator with a threshold of 200mV detects overshoot and
pulls GATE low much harder and hence much faster than
the weaker current limit loop. The V
ACL
/R
S
current limit
loop then takes over and servos the current as previously
described. As before, TIMER runs and shuts down
the
LTC4253B when C
T
reaches 4V.
If C
T
reaches 4V, the LTC4253B latches off with a 5µA
pull-up current source. The LTC4253B circuit breaker latch
is reset by either pulling the RESET pin active high until
TIMER goes low, pulling UV momentarily low, dropping
the input voltage V
IN
below the internal UVLO threshold
or pulsing TIMER momentarily low with a switch.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher voltage
supply, transient currents caused by faults on adjacent
circuit boards sharing the same power bus or the inser-
tion of non-hot swappable products could cause higher
than anticipated input current and temporary detection
of an overcurrent condition. The action of TIMER and C
T
rejects these events allowing the LTC4253B to “ride out”
temporary overloads and disturbances that could trip a
simple current comparator and, in some cases, blow a fuse.
(Refer to Block Diagram)
its pins, the area in and around the LTC4253B and all as-
sociated components should be free of any other planes
such as chassis ground, return, or secondary-side power
and ground planes.
V
IN
may be biased with additional current up to 30mA,
to accommodate external loading such as the PWRGD
opto-couplers shown in Figure 2. As an alternative to
running higher current, simply buffer V
IN
with an emitter
follower. A method that cascodes the PWRGD outputs is
shown in Figure 16.
V
IN
is rated to handle 30mA within the thermal limits of
the package, and is tested to survive a 100µs, 100mA
SHUNT REGULATOR
A fast responding shunt regulator clamps the V
IN
pin to
13V (V
Z
). Power is derived from –48RTN by an external
current limiting resistor, R
IN
. A 1µF decoupling capacitor,
C
IN
filters supply transients and contributes a short delay
at start-up.
To meet creepage requirements R
IN
may be split into two
or more series connected units. This introduces a wider
total spacing than is possible with a single component
while at the same time ballasting the potential across the
gap under each resistor. The LTC4253B is fundamentally
a low voltage device that operates with –48V as its refer-
ence ground. To further protect against arc discharge into