Datasheet

LTC4253B
13
4253bf
operaTion
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met:
1. The input voltage V
IN
exceeds V
LKO
(UVLO).
2. The voltage at UV > V
UVHI
.
3. The voltage at OV < V
OVLO
.
4. The input voltage at RESET < 0.8V.
5. The (SENSE – V
EE
) voltage < 50mV (V
CB
)
6. The voltage at SS is < 0.2V (20 • V
OS
)
7. The voltage on the TIMER capacitor (C
T
)
is < 1V (V
TMRL
).
8. The voltage at GATE is < 0.5V (V
GATEL
)
The first four conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
If RESET < 0.8V occurs after the LTC4253B comes out of
UVLO (interlock condition 1) and undervoltage (interlock
condition 2), GATE and SS are released without an initial
TIMER cycle once the other interlock conditions are
met (see Figure 12a). If not, TIMER begins the start-up
sequence by sourcing 5µA into C
T
. If V
IN
, UV or OV falls
out of range or RESET asserts, the start-up cycle stops
and TIMER discharges C
T
to less than 1V, then waits until
the aforementioned
conditions are once again met. If C
T
successfully charges to 4V, TIMER pulls low and both SS
and GATE pins are released. GATE sources 50µA (I
GATE
),
charging the MOSFET gate and associated capacitance.
The SS voltage ramp limits V
SENSE
to control the inrush
current. PWRGD1 pulls active low when GATE is within
2.8V of V
IN
and DRAIN is lower than V
DRNL
. This sets off
the power good sequence in which PWRGD2 and then
PWRGD3 is subsequently pulled low after a delay, adjust-
able through the SQTIMER capacitor C
SQ
or by external
control inputs EN2 and EN3. In this way, external loads
or power modules controlled by the three PWRGD signals
are turned on in a controlled manner without overloading
the power bus.
Tw o modes of operation are possible during the time
the MOSFET is first turned on, depending on the values
of external components, MOSFET characteristics and
nominal design current. One possibility is that the MOS-
FET will turn on gradually so that the inrush into the load
capacitance remains a low value. The output will simply
ramp to –48V and the LTC4253B will fully enhance the
MOSFET. A second possibility is that
the load current
exceeds the soft-start current limit threshold of [V
SS
(t)/
20 – V
OS
]/R
S
. In this case the LTC4253B ramps the output
by sourcing soft-start limited current into the load capaci-
tance. If the soft-start voltage is below 1.2V, the circuit
breaker TIMER is held low. Above 1.2V, TIMER ramps up.
It is important to set the timer delay so that, regardless
of which start-up mode is used, the TIMER ramp is less
than one circuit breaker delay time. If this condition is
not met, the LTC4253B may shut down after one circuit
breaker delay time.
Board Removal
When the board is withdrawn from the card cage, the UV/
OV divider is the first to lose connection. This shuts off
the MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate
there is no arcing.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor R
S
. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop; and 200mV for a fast, feedfor-
ward
comparator which limits peak current in the event
of a catastrophic short-circuit.
If, due to an output overload, the voltage drop across R
S
exceeds 50mV, TIMER sources 200µA into C
T
. C
T
eventu-
ally charges to a 4V threshold and the LTC4253B shuts
off. If the overload goes away before C
T
reaches 4V and
SENSE measures less than 50mV, C
T
slowly discharges
(5µA). In this way the LTC4253B’s circuit breaker function
responds to low duty cycle overloads, and accounts for the
fast heating and slow cooling characteristic of the MOSFET.