Datasheet

LTC4253B
10
4253bf
pin FuncTions
UV (Pin 12): Undervoltage Input. For the LTC4253B, the
threshold at the UV pin is set at 3.225V with 0.3V hyster-
esis. If UV < 2.925V, PWRGD1 pulls high, both GATE and
TIMER pull low. If UV rises above 3.225V, this initiates
an initial timing cycle followed by GATE start-up. The
internal UVLO at V
IN
always overrides UV. A low at UV
resets an internal fault latch. A 1nF to 10nF capacitor at
UV prevents transients and switching noise from affecting
the UV thresholds and prevents glitches at the GATE pin.
TIMER (Pin 13): Timer Input. Timer is used to generate
an initial timing delay at start-up, and to delay shutdown
in the event of an output overload (circuit breaker fault).
Timer starts an initial timing cycle when the following
conditions are met: RESET is low, UV is high, OV is low,
V
IN
clears UVLO, TIMER pin is low, GATE pin is lower
than V
GATEL
, SS < 0.2V, and V
SENSE
– V
EE
< V
CB
. A pull-up
current of 5µA then charges C
T
, generating a time delay.
If C
T
charges to V
TMRH
(4V), the timing cycle terminates.
TIMER quickly pulls low and GATE is activated.
If
SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 200µA pull-up current charg-
ing C
T
. If DRAIN is approximately 7V during this cycle,
the timer pull-up has an additional current of 8 • I
DRN
. If
SENSE drops below 50mV before TIMER reaches 4V, a
5µA pull-down current slowly discharges the C
T
. In the
event that C
T
eventually integrates up to the V
TMRH
(4V)
threshold, the circuit breaker trips, GATE quickly pulls low
and PWRGD1 pulls high. TIMER latches high with a 5µA
pull-up source. This latched fault may be cleared by driv-
ing RESET high until TIMER is pulled low. Other ways of
clearing the fault include pulling the V
IN
pin momentarily
below (V
LKO
– V
LKH
), pulling TIMER low with an external
device or pulling UV below 2.925V.
SQTIMER (Pin 14): Sequencing Timer Input. The sequenc-
ing timer provides a delay t
SQT
for the power good sequenc-
ing. This delay is adjusted by connecting an appropriate
capacitor to this pin. If the SQTIMER capacitor is omitted,
the SQTIMER pin ramps from 0V to 4V in about 300µs.
EN3 (Pin 15): Power Good Status Output Three Enable.
This
is a TT
L compatible input that is used to control the
PWRGD3 output. When EN3 is driven low, PWRGD3 will
go high. When EN3 is driven high, PWRGD3 will go low
provided PWRGD2 has been active for for more than one
power good sequence delay (t
SQT
). EN3 can be used to
control the power good sequence. This pin is internally
pulled low by a 120µA current source.
PWRGD3 (Pin 16): Power Good Status Output Three. Power
good sequence starts with PWRGD1 latching active low.
PWRGD3 will latch active low after EN3 goes high and
after one power good sequence delay t
SQT
provided by
the sequencing timer from the time PWRGD2 goes low,
whichever comes later. PWRGD3 is reset by PWRGD1
going high or EN3 going low. This pin is internally pulled
high by a 50µA current source.