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LTC4253B

4253bf

–48V/2.5A Hot Swap Controller

Start-Up Behavior

Typical applicaTion

FeaTures DescripTion

–48V Hot Swap Controller

with Sequencer

The LTC

4253B negative voltage Hot Swap™ controller

allows a board to be safely inserted and removed from a

live backplane. Output current is controlled by three stages

of current-limiting: a timed circuit breaker, active current

limiting and a fast feedforward path that limits peak cur-

rent under worst-case catastrophic fault conditions. The

LTC4253B latches off after a circuit fault.

Adjustable undervoltage and overvoltage detectors dis-

connect the load whenever the input supply exceeds the

desired operating range. The LTC4253B’s supply input is

shunt-regulated, allowing safe operation with very high

supply voltages. A multifunction timer delays initial start-up

and controls the circuit breaker’s response time. The circuit

breaker’s response time can be accelerated by sensing

excessive MOSFET drain voltage, keeping the MOSFET

within its safe operating area (SOA). An adjustable soft-

start circuit controls MOSFET inrush current at start-up.

Three power good outputs are sequenced by an adjustable

timer and two ENABLE inputs to enable external power

modules at start-up or disable them if the circuit breaker

trips. The LTC4253B improves the ruggedness of the

LTC4253 shunt regulator.

applicaTions

Allows Safe Board Insertion and Removal from a

Live –48V Backplane

Floating Topology Permits Very High Voltage

Operation

Adjustable Analog Current Limit with Breaker Timer

Ideal for Tw o Battery Feeds

Fast Response Time Limits Peak Fault Current

Three Sequenced Power Good Outputs

Improved Ruggedness Shunt Regulator

Adjustable Soft-Start Current Limit

Adjustable Timer with Drain Voltage Accelerated

Response

Latchoff After Fault

Available in a 16-Pin SSOP Package

–48V Distributed Power Systems

Negative Power Supply Control

Central Office Switching

High Availability Servers

Disk Arrays

L, LT , LT C , LT M, Linear Technology and the Linear logo are registered trademarks and Hot

Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of

their respective owners.

5.6k 5.6k 5.6k

†

PWRGD1

EN2

EN3

LTC4253B

LOAD1

PWRGD2

PWRGD3

DRAIN

GATE

SQTIMER

SENSETIMER

LOAD2

LOAD3

2.5k

15k(1/4W)/6

RESET

4253b TA01

10Ω

0.02Ω

IRF530S

*DIODES, INC.

†

MOC207

††

RECOMMENDED FOR HARSH ENVIRONMENTS.

18nF

0.33µF

0.1µF

68nF

10nF

100µF

B3100*

402k

–48V A

–48V B

–48V RTN

B3100*

†

32.4k

1µF

††

DDZ13B*

GATE

10V

SENSE

50mV

OUT

50V

1ms/DIV

4253b TA01b

Summary of content (32 pages)

PAGE 1
LTC4253B –48V Hot Swap Controller with Sequencer Features n n n n n n n n n n Description Allows Safe Board Insertion and Removal from a Live –48V Backplane Floating Topology Permits Very High Voltage Operation Adjustable Analog Current Limit with Breaker Timer Ideal for Two Battery Feeds Fast Response Time Limits Peak Fault Current Three Sequenced Power Good Outputs Improved Ruggedness Shunt Regulator Adjustable Soft-Start Current Limit Adjustable Timer with Drain Voltage Accelerated Response Latchof
PAGE 2
LTC4253B Absolute Maximum Ratings Pin Configuration (Note 1), All voltages referred to VEE TOP VIEW Current into VIN (100µs Pulse)..............................100mA Current into DRAIN (100µs Pulse)..........................20mA VIN, DRAIN Minimum Voltage.................................–0.3V Input/Output (Except SENSE and DRAIN) Voltage.................................... –0.3V to 16V SENSE Voltage............................................ –0.6V to 16V Current Out of SENSE (20µs Pulse)...............
PAGE 3
LTC4253B Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS VZ VIN – VEE Zener Voltage IIN = 2mA RZ VIN – VEE Zener Dynamic Impedance IIN = (2mA to 30mA) IIN VIN Supply Current UV = OV = 4V, VIN = (VZ – 0.3V) ● 0.8 2 VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising VIN) ● 9.2 11.5 V 1 1.5 V ● MIN TYP MAX UNITS 11.5 13 14.
PAGE 4
LTC4253B Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER VTMRL TIMER Pin Voltage Low Threshold ITMR TIMER Pin Current CONDITIONS Timer On (Initial Cycle/Latchoff, Sourcing), VTMR = 2V MIN TYP MAX ● 0.8 1 1.
PAGE 5
LTC4253B Typical Performance Characteristics VZ vs Temperature 14.5 IIN vs VIN IIN vs Temperature 1000 IIN = 2mA 1000 950 14.0 900 100 13.0 10 TA = –40°C TA = 85°C TA = 25°C TA = 125°C 850 IIN (µA) VZ (V) IIN (mA) 13.5 800 750 700 650 1 12.5 VIN = VZ – 0.3V 600 550 12.0 –55 –35 –15 0.
PAGE 6
LTC4253B Typical Performance Characteristics IGATE (FCL, Sink) vs Temperature 400 UV/OV = 4V TIMER = 0V VSENSE – VEE = 0.3V VGATE = 1V 350 300 14.0 13.5 VGATE vs Temperature UV/OV = 4V TIMER = 0V VSENSE = VEE IIN = 2mA 0.9 0.8 150 12.5 12.0 11.5 0.5 0.4 0.3 11.0 0.2 50 10.5 0.1 10.0 –55 –35 –15 UV Threshold vs Temperature 3.375 UV/OV = 4V VGATEH = VIN – VGATE IIN = 2mA IIN = 2mA UV THRESHOLD (V) 2.6 VUVH 3.175 3.075 2.975 VUVL 2.4 2.875 2.2 2.
PAGE 7
LTC4253B Typical Performance Characteristics ITMR (Initial Cycle, Sourcing) vs Temperature 9 240 IIN = 2mA VTMR = 2V ITMR (µA) 6 5 4 3 210 200 190 0 –55 –35 –15 160 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5.0 4.0 8.4 3.5 8.2 3.0 2.0 1.5 7.4 1.0 7.2 0.5 7.0 –55 –35 –15 IIN = 2mA 7.8 IDRN = 50µA 7.6 2.35 5 25 45 65 85 105 125 TEMPERATURE (°C) 2.20 –55 –35 –15 VPGL vs Temperature 3.0 IIN = 2mA 6.6 IPG = 10mA 2.0 0.1 TA = 85°C 0.01 TA = 125°C 0.0001 6.
PAGE 8
LTC4253B Typical Performance Characteristics IPGH vs Temperature tSS vs Temperature 60 300 290 IIN = 2mA SS PIN FLOATING VSS RAMPS FROM 0.2V TO 2V 450 56 280 54 270 350 52 260 300 50 48 250 240 250 200 46 230 150 44 220 100 42 210 50 40 –55 –35 –15 200 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4253b G28 IIN = 2mA VSQTMR RAMPS FROM 0.5V TO 3.
PAGE 9
LTC4253B Pin Functions RESET (Pin 5): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs high. The RESET pulse must be wide enough to discharge any voltage on the TIMER pin below VTMRL. After the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in Interlock Conditions in the Operation section. SS (Pin 6): Soft-Start Pin.
PAGE 10
LTC4253B Pin Functions UV (Pin 12): Undervoltage Input. For the LTC4253B, the threshold at the UV pin is set at 3.225V with 0.3V hysteresis. If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at VIN always overrides UV. A low at UV resets an internal fault latch.
PAGE 11
LTC4253B Block Diagram VIN 4 VIN VIN – 50µA 4V 5µA VEE PWRGD1 3 + 14 SQTIMER VEE EN2 1 VIN – 120µA 50µA VEE + PWRGD2 2 SQTIMER DELAY VEE – 10 DRAIN VEE EN3 15 0.33V VIN VIN + 120µA 50µA 2.39V 8× 1× VEE PWRGD3 16 1× VIN SQTIMER DELAY 6.15V 1× VEE 50µA 9 GATE VEE VIN 6.15V VEE – OV 11 + + UV 12 – – VIN 2.925V + 5µA 4V – + – – + LOGIC 2.8V 0.
PAGE 12
LTC4253B Operation Hot Circuit Insertion conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset.
PAGE 13
LTC4253B Operation Interlock Conditions A start-up sequence commences once these “interlock” conditions are met: 1. The input voltage VIN exceeds VLKO (UVLO). 2. The voltage at UV > VUVHI. 3. The voltage at OV < VOVLO. 4. The input voltage at RESET < 0.8V. 5. The (SENSE – VEE) voltage < 50mV (VCB) 6. The voltage at SS is < 0.2V (20 • VOS) 7. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL). 8. The voltage at GATE is < 0.
PAGE 14
LTC4253B Operation Higher overloads are handled by an analog current limit loop. If the drop across RS reaches VACL, the current limiting loop servos the MOSFET gate and maintains a constant output current of VACL/RS. In current limit mode, VOUT (MOSFET drain-source voltage drop) typically rises and this increases MOSFET heating. If VOUT > VDRNCL, connecting an external resistor, RD between VOUT and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor.
PAGE 15
LTC4253B Applications Information pulse. To protect VIN against damage from higher amplitude spikes, clamp VIN to VEE with a 13V Zener diode. Star connect VEE and all VEE-referred components to the sense resistor Kelvin terminal as illustrated in Figure 2, keeping trace lengths between VIN, CIN, DIN and VEE as short as possible. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis VLKH.
PAGE 16
LTC4253B Applications Information The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at TIMER to provide timing for the LTC4253B. Four different charging and discharging modes are available at TIMER: 1. 5µA slow charge; initial timing delay. 2. (200µA + 8 • IDRN) fast charge; circuit breaker delay. 3. 5µA slow discharge; circuit breaker “cool-off.” 4.
PAGE 17
LTC4253B Applications Information Power Good Sequencing After the initial TIMER cycle, GATE ramps up to turn on the external MOSFET which in turn pulls DRAIN low. When GATE is within 2.8V of VIN and DRAIN is lower than VDRNL, the power good sequence starts with PWRGD1 pulling active low. This starts off a 5µA pull-up on the SQTIMER pin which ramps up until it reaches the 4V threshold then pulls low. When the SQTIMER pin floats, this delay tSQT is about 300µs.
PAGE 18
LTC4253B Applications Information Sense The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When SENSE exceeds 50mV, the CB comparator activates the 200µA TIMER pull-up. At 100mV the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control.
PAGE 19
LTC4253B Applications Information MOSFET Selection The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current but the opposite may not be true. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves.
PAGE 20
LTC4253B Applications Information Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the RSSCSS response. An overconservative but simple approach begins with the maximum circuit breaker current, given by: VCB(MAX) ICB(MAX) = (14) RS where VCB(MAX) is 60mV. From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by: t SOA(MAX) CSS = (15) 0.
PAGE 21
LTC4253B Applications Information Sense Resistor Considerations For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4253B’s VEE and SENSE pins are strongly recommended. The drawing in Figure 6 illustrates the correct way of making connections between the LTC4253B and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors.
PAGE 22
LTC4253B Applications Information VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, RESET < 0.
PAGE 23
LTC4253B Applications Information Live Insertion with Short Pin Control of UV/OV connections are firmly established before the LTC4253B is activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In In the example shown in Figure 8, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin.
PAGE 24
LTC4253B Applications Information addition, the internal logic checks for OV < VOVHI, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. When all conditions are met, initial timing starts and the TIMER capacitor is charged by a 5µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged.
PAGE 25
LTC4253B Applications Information UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.
PAGE 26
LTC4253B Applications Information OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 VOVHI OV 5 67 8 9 VOVLO VTMRH 200µA + 8 • IDRN TIMER 5µA 50µA GATE VGATEL 5µA VIN – VGATEH 50µA 20 • (VACL + VOS) 20 • (VCB + VOS) SS 20 • VOS VACL VCB SENSE GATE START-UP 4253b F10 Figure 10.
PAGE 27
LTC4253B Applications Information Resetting a Fault Latch A latched circuit breaker fault of the LTC4253B has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high until the TIMER pin is pulled below VTMRL(1V) as shown in Figure 12b. After the RESET pulse, SS and GATE ramp up without an initial timing cycle provided the interlock conditions are satisfied. rent is added to the TIMER pull-up current of 200µA.
PAGE 28
SS GATE TIMER VGATEL VTMRL VTMRH RESET UV/OV VIL (12a) Reset Forcing Start-Up without Initial TIMER Cycle VUVHI RESET PULSE WIDTH MUST FULLY DISCHARGE TIMER VIH VUVHI VIL RESET UV/OV Figure 12.
PAGE 29
LTC4253B Applications Information CB TIMES-OUT 12 34 1 VTMRH 200µA + 8 • IDRN TIMER 2 VTMRH 200µA + 8 • IDRN TIMER 5µA GATE GATE SS VACL SENSE VFCL SENSE VCB VACL VCB VOUT VOUT VDRNCL DRAIN DRAIN PWRGD1 PWRGD1 4253b F13 (13a) Analog Current Limit Fault (13b) Fast Current Limit Fault Figure 13.
PAGE 30
LTC4253B Applications Information Power Limit Circuit Breaker Figure 15 shows the LTC4253B in a power limit circuit breaking application. The SENSE pin is modulated by board voltage VSUPPLY. The D1 Zener voltage, VZ, is set to be the same as the lowest operating voltage, VSUPPLY(MIN) = 43V.
PAGE 31
LTC4253B Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ±.0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ±.004 × 45° (0.38 ±0.10) .007 – .0098 (0.178 – 0.
PAGE 32
LTC4253B Typical Application + RIN 10k 20k(1/4W)/2 – 48V RTN (LONG PIN) VIN CIN 1µF – 48V RTN (SHORT PIN) VIN EN2 EN3 R2 402k 1% RESET (LONG PIN) OV PWRGD1 UV PWRGD2 RESET PWRGD3 C1 10nF LTC4253B R7 100k C3 0.1µF EN CSQ 0.1µF TIMER VEE POWER MODULE 2 EN POWER MODULE 3 EN † † RD 1M 4253b F16 VOUT R3 38.3k SQTIMER POWER MODULE 1 † SS R8 47k Q1 IRF530S GATE SENSE CT 1µF – 48V (LONG PIN) R6 100k DRAIN CSS 68nF R1 32.