Datasheet

LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
17
4252b12f
APPLICATIONS INFORMATION
2.5% or more will eventually trip the circuit breaker and
shut down the LTC4252. Figure 5 shows the circuit breaker
response time in seconds normalized to 1µF for I
DRN
=
0µA. The asymmetric charging and discharging of C
T
is
a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
t
C
T
(µF)
=
4
235.8+8 •I
DRN
( )
•D–5.8




(4)
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8µA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry ver-
sion), a shutdown cooling cycle begins if TIMER reaches
the 4V threshold. TIMER starts with a 5.8µA pull-down
until it reaches the 1V threshold. Then, the 5.8µA pull-up
turns back on until TIMER reaches
the 4V threshold. Four
5.8µA pull-down cycles and three 5.8µA pull-up cycles
occur between the 1V and 4V thresholds, creating a time
interval given by:
t
SHUTDOWN
=
7 •3V •C
T
5.8µA
(5)
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load.
If SS floats, an internal current source ramps SS from 0V
to 2.2V for the LTC4252B or 0V
to 1.4V for the LTC4252C
in about 230µs. Connecting an external capacitor C
SS
from SS to ground modifies the ramp to approximate an
RC response of:
V
SS
(t)≈V
SS
• 1–e
–
t
R
SS
• C
SS
















(6)
An internal resistive divider (95k/5k for the LTC4252B or
47.5k/2.5k for the LTC4252C) scales V
SS
(t) down by 20
times to give the analog current limit threshold:
V
ACL
(t)=
V
SS
(t)
20
–V
OS
(7)
This allows the inrush current to be limited to V
ACL
(t)/R
S
.
The offset voltage, V
OS
(10mV), ensures C
SS
is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault
times out.
GATE
GATE is pulled low to V
EE
under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58µA current source charges the MOSFET gate and
any associated external capacitance. V
IN
limits the gate
drive to no more than 14.5V.
Gate-
drain capacitance (C
GD
) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
IN
FAULT DUTY CYCLE (%)
0 20 40 60 80 100
NORMALIZED RESPONSE TIME (s/µF)
10
1
0.1
0.01
4252B12 F05
=
4
[(235.8 + 8 • I
DRN
) • D – 5.8]
t
C
T
(µF)
I
DRN
= 0µA
Figure 5. Circuit-Breaker Response Time