Datasheet
LTC4223-1/LTC4223-2
4
422312f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
TMR(UP)
TIMER Pull-Up Current V
TIMER
= 1V, Initial Timing Cycle
V
TIMER
= 0V, In AUX Fault Mode
V
TIMER
= 0V, In 12V Fault Mode
●
●
●
–7
–7
–140
–10
–10
–200
–13
–13
–260
μA
μA
μA
I
TMR(DN)
TIMER Pull-Down Current V
TIMER
= 2V, No Faults
V
TIMER
= 2V, In Reset Mode
●
●
1.3
2
2
8
2.6
16
μA
mA
Open Drain Outputs
V
OL
Output Low Voltage (
⎯
F
⎯
A
⎯
U
⎯
L
⎯
T,
⎯
1
⎯
2
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D,
⎯
A
⎯
U
⎯
X
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D)
I
OL
= 3mA
●
0.15 0.4 V
V
OH
Output High Voltage (
⎯
F
⎯
A
⎯
U
⎯
L
⎯
T,
⎯
1
⎯
2
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D,
⎯
A
⎯
U
⎯
X
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D)
(Note 5)
●
V
CC
– 1 V
I
PU
Output Pin Pull-Up Current (
⎯
F
⎯
A
⎯
U
⎯
L
⎯
T,
⎯
1
⎯
2
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D,
⎯
A
⎯
U
⎯
X
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D)
V
PU
= 1.5V
●
–6 –10 –14 μA
Logic Inputs
V
IN(TH)
Logic Input Threshold (12ON, AUXON,
⎯
E
⎯
N)
●
0.8 2 V
I
IN(LEAK)
Input Leakage Current (12ON, AUXON) V
IN
= V
CC
●
±1 μA
R
PU
⎯
E
⎯
N Pin Pull-Up Resistance
●
60 100 140 kΩ
Other Pin Functions
I
12VSENSE
12V
SENSE
Pin Input Current V
12VSENSE
= 12V
●
10 50 100 μA
I
12VOUT
12V
OUT
Pin Input Current Gate Drive On, V
12VOUT
= 12V
●
20 50 100 μA
R
OUT(DIS)
OUT Pin Discharge Resistance
12V
OUT
AUXOUT
Gate Drive Off
V
12VOUT
= 6V
V
AUXVOUT
= 2V
●
●
400
375
800
750
1600
1500
Ω
Ω
Propagation Delays
t
CB
AUX Circuit Breaker Trip Delay After Power Up
●
12 25 50 μs
t
PHL(SENSE)
Sense Voltage, (12V
IN
– 12V
SENSE
)
High to 12V
GATE
Low
ΔV
SENSE
= 300mV, C
12VGATE
= 10nF
ΔV
SENSE
= 100mV, C
12VGATE
= 10nF
●
●
0.5
5
1
12
μs
μs
t
PHH(AUXON)
AUXON High to AUXOUT High
●
15 30 μs
t
PHH(12ON)
12ON High to 12V
GATE
High
●
30 60 μs
t
RST(ON)
Input Low (12ON, AUXON) to
⎯
F
⎯
A
⎯
U
⎯
L
⎯
T High
●
20 40 μs
t
RST(VCC)
V
CC
Low to
⎯
F
⎯
A
⎯
U
⎯
L
⎯
T High
●
80 150 μs
t
PLL(UVLO)
12V
IN
Low to 12V
GATE
Low
●
61218 μs
AUXIN Low to
⎯
A
⎯
U
⎯
X
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D High
●
61218 μs
t
PHL(GATE)
⎯
E
⎯
N High to 12V
GATE
Low
●
20 40 μs
t
PLH(PG)
12V
OUT
Low to
⎯
1
⎯
2
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D High
●
20 40 μs
AUXOUT Low to
⎯
A
⎯
U
⎯
X
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D High
●
20 40 μs
t
P(12IMON)
Input Sense Voltage Step to 12IMON
Propagation Delay
ΔV
SENSE
= 100mV
●
26 μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to GND unless
otherwise specifi ed.
Note 3: An internal clamp limits the 12V
GATE
pin to a minimum of 4.5V
above 12V
OUT
. Driving this pin to voltages beyond the clamp may damage
the device.
Note 4: For the DFN package, the AUX switch on resistance, R
DS(ON)
limit
is guaranteed by correlation to wafer test measurements.
Note 5: The output pins
⎯
F
⎯
A
⎯
U
⎯
L
⎯
T,
⎯
1
⎯
2
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D and
⎯
A
⎯
U
⎯
X
⎯
P
⎯
G
⎯
O
⎯
O
⎯
D have an internal
pull-up to V
CC
of 10μA. However, an external pull-up resistor may be used
when faster rise time is required or for V
OH
voltages greater than V
CC
.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are T
A
= 25°C, V
CC
= 3.3V, V
AUXIN
= 3.3V, V
12VIN
=12V, unless otherwise specifi ed. (Note 2)