Datasheet

LTC4222
5
4222fb
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
2
C Interface
V
ADR(H)
ADR0, ADR1, ADR2 Input High Voltage
l
INTV
CC
– 0.8
INTV
CC
– 0.4
INTV
CC
– 0.2
V
I
ADR(IN,Z)
ADR0, ADR1, ADR2 Hi-Z Input Current ADR0, ADR1, ADR2 = 0.8V,
INTV
CC
– 0.8V
l
5 0 –5 µA
V
ADR(L)
ADR0, ADR1, ADR2 Input Low Voltage
l
0.2 0.4 0.8 V
I
ADR(IN)
ADR0, ADR1, ADR2 Input Current ADR0, ADR1, ADR2 = 0V, INTV
CC
l
–80 80 µA
V
ALERT(OL)
ALERT Output Low Voltage I
ALERT
= 3mA
l
0.2 0.4 V
I
ALERT(OH)
ALERT Input Current ALERT = INTV
CC
l
±1 µA
V
SDA,SCL(TH)
SDA, SCL Input Threshold
l
1.5 1.7 1.9 V
I
SDA,SCL(OH)
SDA, SCL Input Current SCL, SDA = INTV
CC
l
±1 µA
V
SDA(OL)
SDA Output Low Voltage I
SDA
= 3mA
l
0.2 0.4 V
I
2
C Interface Timing
f
SCL(MAX)
SCL Clock Frequency Operates with f
SCL
≤ f
SCL(MAX)
400 1000 kHz
t
BUF(MIN)
Bus Free Time Between Stop/Start Condition 0.12 1.3 µs
t
HD,STA(MIN)
Hold Time After (Repeated) Start Condition 100 600 ns
t
SU,STA(MIN)
Repeated Start Condition Set-Up Time 30 600 ns
t
SU,STO(MIN)
Stop Condition Set-Up Time 140 600 ns
t
HD,DAT(MIN)
Data Hold Time (Input) 30 100 ns
t
HD,DATO
Data Hold Time (Output) 300 600 900 ns
t
SU,DAT(MIN)
Data Set-Up Time 30 600 ns
t
SP
Suppressed Spike Pulse Width 50 110 250 ns
t
RST
Stuck-Bus Reset Time SCL or SDA Held Low 25 32 40 ms
C
X
SCL, SDA Input Capacitance SDAI Tied to SDAO (Note 5) 10 pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: Integral Nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specifications are
measured from 1/4, 1/2, 3/4 areas of the quantization band.
Note 5: Guaranteed by design and not subject to test.