Datasheet

14
LTC4221
4221fa
sequential power up from time points 4 to 8 and a
sequential power-down programmed from time points 9
to 11. To achieve this the circuit requires the functionality
of the PWRGD1 pin and will be featured in the next section.
The circuit in Figure 2a sits on a daughter board with
staggered pins on its edge connectors. Supply voltage and
ground connections are wired to long-edge connector
pins while both ON pins are connected to a short-edge
connector pin through a resistive divider. Until the con-
nectors are fully mated, ON1 is pulled low and holds both
channels in the reset state. When the connectors have
properly seated, the ON pins are pulled above 0.851V and
an initial timing cycle starts. This cycle is restarted by any
transitions on the ON pins across their off thresholds and
adds a further delay for the plug-in transients to die off
before allowing a start-up cycle. The Typical Application
circuit on the first page of this data sheet shows similar
considerations in the design of its PCB edge connectors,
and the resistive dividers connected to ON1 and ON2 act
as an external UVLO to override the internal one. An RC
filter can be added at the ON1 pin to increase the delay time
at card insertion to allow bus supply transients to stabilize.
FB and PWRGD Pin Functions
Each FB pin is used to detect undervoltage and overvoltage
in its channel output voltage (V
OUT
) through a resistive
divider. Each FB pin has an undervoltage comparator with
a high-to-low threshold of 0.617V and 3mV hysteresis.
The output of this comparator controls the channel’s
open-drain PWRGD output. During UVLO, both PWRGD
pins are pulled low by internal N-channel MOSFET pull-
downs. As both channels come out of UVLO, control of
PWRGD1 is passed to FB1and control of PWRGD2 to FB2.
Each PWRGD pin can be connected to a pull-up resistor to
0.821V
100μA
V
CC n
12 34 5 67 8 91011
ON1
TIMER
GATE1
V
OUT1
PWRGD1
ON2
GATE2
UVLO INITIAL
TIMING
RESET
V
OUT2
V
CC n (UVL)
0.851V
0.821V
0.4V
1.234V
20μA
100μA
DISCHARGE
BY LOAD
DISCHARGE
BY LOAD
4221 F03
20μA
9.5μA
9.5μA
V
TH
0.851V
V
TH
V
FB1
= 0.620V
V
FB1
= 0.617V
CHANNEL 1
START-UP
CHANNEL 2
START-UP
CHANNEL 1 OFF
CHANNEL 2 NORMAL
NORMAL OFF
1.9μA
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Sequential Power On/Off Timing Waveforms