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LTC4221

4221fa

Dual Hot Swap Controller/

Power Sequencer with Dual Speed,

Dual Level Fault Protection

■

Allows Safe Board Insertion and Removal from a

Live Backplane

■

Configurable Power Supply Sequencing

■

Soft-Start with Current Foldback Limits Inrush

Current

■

No External Gate Capacitor Required

■

Adjustable Dual Level Circuit Breaker Protection

■

Controls Supply Voltages from 1V to 13.5V

■

Independent N-Channel MOSFET High Side Drivers

■

Pin Monitors V

OUT

for Overvoltage Protection

■

Latch Off or Automatic Retry on Current Fault

■

FAULT and PWRGD Outputs

■

Narrow 16-Pin SSOP Package

■

Electronic Circuit Breaker

■

Power Supply Sequencing

■

Live Board Insertion and Removal

■

Industrial High Side Switch/Circuit Breaker

The LTC

4221 is a 2-channel Hot Swap

controller that

allows a board to be safely inserted and removed from a

live backplane. Using two independent high side gate

drivers to control two external N-channel pass transistors,

the output voltages can be ramped up with current foldback

to limit the inrush current during the start-up period. No

external compensation capacitors are required at the

GATE pins. The two channels can be configured to ramp up

and down separately or simultaneously for supply volt-

ages ranging from 2.7V to 13.5V and 1V to 13.5V for

channels 1 and 2 respectively.

Each channel has two current limit comparators that

provide dual level and dual speed overcurrent circuit

breaker protection after the start-up period. If any current

sense voltage exceeds 100mV for 1μs or 25mV for the

timeout delay (set by the C

FILTER

at the FILTER pin), then

the FAULT latch is set and both GATE pins are pulled low.

The FB pins monitor the respective channel output volt-

ages and provide the inputs for the PWRGD comparators

as well as overvoltage protection.

Hot Swap is a trademark of Linear Technology Corporation.

2-Channel Hot Swap Controller

FEATURES

DESCRIPTIO

APPLICATIO S

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

ON2

FAULT

GND

LTC4221

FB2

PWRGD2

PWRGD1

PWRGD2

OUT1

3.3V/5A

OUT2

2.5V/5A

PWRGD1

FB1

LONG

SHORT

GND

FAULT

LONG

*SMAJ10 (OPTIONAL)

SHORT

TIMER FILTER

ON1

CC1

SENSE1 GATE1 V

CC2

SENSE2 GATE2

SHORT

CC1

3.3V

CC2

2.5V

BACKPLANE

CONNECTOR

(FEMALE)

PCB EDGE

CONNECTOR

(MALE)

10Ω

21k

13.3k

10k

10Ω

14.3k

IRF7413

5.11k

10k

20k

5.11k

4221 TA01

100nF

1nF

470nF

100nF

IRF7413

0.004Ω

Summary of content (28 pages)

PAGE 1
LTC4221 Dual Hot Swap Controller/ Power Sequencer with Dual Speed, Dual Level Fault Protection U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®4221 is a 2-channel Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using two independent high side gate drivers to control two external N-channel pass transistors, the output voltages can be ramped up with current foldback to limit the inrush current during the start-up period.
PAGE 2
LTC4221 U U U U W W W ABSOLUTE MAXIMUM RATINGS PI CO FIGURATIO (Note 1) Supply Voltage (VCCn) ............................................ 17V SENSEn Pins ............................ – 0.3V to (VCCn + 0.3V) FB, ON Pins .............................. – 0.3V to (VCC1 + 0.3V) TIMER Pin .................................................. – 0.3V to 2V GATE Pins (Note 3) ................................... – 0.3V to 21V PWRGD, FAULT, FILTER Pins ................... – 0.
PAGE 3
LTC4221 ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IGATE(UP) GATEn Output Current VON1 = VON2 = 2V, VGATEn = 0V ● –7 –9.5 –12 μA IGATE(DN) GATEn Output Current VON1 = VON2 = 0.6V, VGATEn = 3.3V ● 75 100 125 μA IGATE(FSTDN) GATEn Output Current UVLO with VGATEn = 3.
PAGE 4
LTC4221 ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS TYP MAX tP(FAULT-GATE) FAULT Low to GATEn Discharging VFAULT = 3.
PAGE 5
LTC4221 U W TYPICAL PERFOR A CE CHARACTERISTICS VSENSE(SC) vs VCC1 VSENSE(FC) vs Temperature VCC1 = 5V VCC2 = 3.3V 100.5 100.0 25.6 25.2 25.0 24.8 24.6 99.5 25.0 24.6 24.2 50 25 75 0 TEMPERATURE (°C) 100 125 0 4 2 6 8 10 12 14 VCC1 = 5V VCC2 = 3.3V 25 TA = 25°C –11 0 0.3 0.4 VFB (V) 0.5 0.6 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 100 50 25 75 0 TEMPERATURE (°C) 100 97 –50 –25 125 15 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 125 16 VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.
PAGE 6
LTC4221 U W TYPICAL PERFOR A CE CHARACTERISTICS ΔVGATE2 (VGATE2 – VCC1) vs Temperature VGATE(OV) vs Temperature 0.420 VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V 14 VCC2 = 1V, TA = 25°C 0.425 RISING 0.410 VGATE(OV) (V) 12 ΔVGATE2 (V) VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V VCC2 = 1V TIMER = 0.5V 0.415 VON(RESET) vs VCC1 0.430 10 8 0.420 0.405 VON(RESET) (V) 16 0.400 0.395 0.390 0.415 0.410 0.405 0.385 FALLING 6 0.400 0.
PAGE 7
LTC4221 U W TYPICAL PERFOR A CE CHARACTERISTICS IFILTER(UP) vs Temperature VFB(OV) vs Temperature 0.825 –88 VCC1 = 5V 0.824 VCC2 = 3.3V –93 IFILTER(UP) (μA) 0.822 0.821 0.820 0.819 0.818 0.817 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 1.95 –103 –108 –113 50 25 0 75 TEMPERATURE (°C) 100 50 25 75 0 TEMPERATURE (°C) 4221 G25 100 1.65 –50 –25 125 –1.6 VCC2 = 1V 1.244 V GATE1 = 0.2V 1.242 VCC2 = 1V VTMR = 0.25V –1.7 VCC2 = 1V –17.5 VTMR = 0.25V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V –18.0 1.232 1.
PAGE 8
LTC4221 U W TYPICAL PERFOR A CE CHARACTERISTICS VFAULT(TH) vs VCC1 IFAULT(UP) vs Temperature –3.3 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V VCC2 = 1V VFAULT = 1.5V RISING 0.850 0.86 VFAULT(TH) (V) –3.7 –3.9 0.840 0.835 0.830 0.825 0.84 0.83 FALLING 0.810 50 25 75 0 TEMPERATURE (°C) 100 0 125 FALLING 0.81 0.815 –4.5 –50 –25 2 6 4 8 10 12 14 16 0.80 –50 –25 VCC1 (V) VPWRGD(OL)/VFAULT(OL) vs Temperature 18 0.450 VCC2 = 1V TIMER = 0.5V 0.250 0.200 0.150 0.
PAGE 9
LTC4221 U U U PI FU CTIO S GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high side gate drive of an external N-channel MOSFET. When VON1 < 0.821V, GATE1 is held low by a 100μA current source. When VON1 > 0.851V, an initial timing cycle is followed by a start-up cycle when an internal charge pump provides a 9.5μA pull-up to ramp up GATE1 with inrush current limiting. UVLO, overvoltage, overcurrent and externally generated faults override the ON1 pin and pull GATE1 low.
PAGE 10
LTC4221 W BLOCK DIAGRA VCC1 CHARGE PUMP 1 CPO1 CHARGE PUMP 2 CPO2 VCC1 OSCILLATOR VCC1 ON1 0.821V 0.4V – + 0.821V – + 1 ON2 16 VCC1 105μA FILTER VCC2 + 8 – 1.24V UVLO 20μA 1.9μA ON1 COMPARATOR 9 TIMER ON2 COMPARATOR FTRHI FILTER COMPARATOR SYSTEM CONTROL LOGIC + TMRHI – TMRHI COMPARATOR 1.8μA 1.234V + TMRLO VCC1 0.4V – TMRLO COMPARATOR 3.8μA 0.816V FAULT VCC1 VCC1 7 + FAULT_LO – 10 GND FAULT COMPARATOR CPO1 12V 9.
PAGE 11
LTC4221 U OPERATIO Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current may damage the connector pins and glitch the power bus, causing other boards in the system to reset. The LTC4221 is designed to turn on and off a circuit board’s supply voltages in a controlled manner, allowing insertion or removal without glitches or connector damage.
PAGE 12
LTC4221 U OPERATIO VCCn CLEARS VCCn(UVL) ON1 > VON(RESET) + ΔVON(RESETHYST) ELECTRONIC CIRCUIT BREAKER ARMED, CHECK FILTER < VFILTER(TH), FAULT > VFAULT(TH) + ΔVFAULT(HYST) ON2 > VON(OFF), + ΔVON(OFFHYST), CHECK GATE < VGATE(OV), TIMER < 0.4V CHANNEL 1 SLOW COMPARATOR ARMED ON1 > VON(OFF) + ΔVON(OFFHYST), CHECK GATE < VGATE(OV), TIMER < 0.4V 1 VCCn 3 2 CHANNEL 2 SLOW COMPARATOR ARMED 4 56 7 8 9 10 11 12 13 14 15 VCCn(UVL) VTMR(H) 1.
PAGE 13
LTC4221 U W U U APPLICATIO S I FOR ATIO Undervoltage Lockout In addition to its global reset function, ON1 also serves as an on/off switch for channel 1. ON2 performs the same role for channel 2. Both pins have an off comparator with a high-to-low threshold of 0.821V and 30mV hysteresis. With these, ON1 and ON2 can be used to force a simultaneous or sequential power-up/power-down of the two channels. A simultaneous power-up and power-down is shown in Figure 2b.
PAGE 14
LTC4221 U W U U APPLICATIO S I FOR ATIO 1 2 3 4 5 6 7 8 9 10 11 VCCn VCCn(UVL) ON1 0.851V 0.821V 0.4V 1.234V 1.9μA TIMER 20μA 20μA 9.5μA GATE1 100μA VTH VFB1 = 0.620V VOUT1 VFB1 = 0.617V DISCHARGE BY LOAD PWRGD1 0.851V ON2 0.821V 9.5μA GATE2 100μA VTH DISCHARGE BY LOAD VOUT2 4221 F03 UVLO INITIAL TIMING CHANNEL 1 START-UP CHANNEL 2 START-UP RESET NORMAL OFF CHANNEL 1 OFF CHANNEL 2 NORMAL Figure 3.
PAGE 15
LTC4221 U W U U APPLICATIO S I FOR ATIO R4 pull-up on PWRGD1. Its is only when channel 1 is powered off and VOUT1 discharges below its undervoltage threshold at time point 10 that PWRGD1’s internal N-channel MOSFET pull-down is triggered and ON2 goes low. At time point 11, ON2 trips its off threshold and GATE2 pulls low with a 100μA pull-down, powering off channel 2. generate a logic high output to indicate that VOUT is valid.
PAGE 16
LTC4221 U W U U APPLICATIO S I FOR ATIO ON1 clears its off threshold and the initial timing cycle is complete, the GATE1 pin is pulled up by a 9.5μA current source connected to the charge pump output during the channel start-up cycle. GATE1 can be servoed by adjusting the ramp up current to <9.5μA to control the inrush current to the load during start-up. ON2 controls GATE2 in a similar manner but is overwritten by ON1’s global reset function.
PAGE 17
LTC4221 U W U U APPLICATIO S I FOR ATIO The fast comparators trip the circuit breaker to protect against fast load overcurrents if VRSENSE is greater than VSENSE(FC) (100mV) for 1μs. The response time of each fast comparator is fixed at 1μs nominal. The timing diagram in Figure 9 illustrates the operation of the LTC4221 when the load current conditions cause VRSENSE of channel 1 to exceed 100mV for more than 1μs between time points 7 and 8.
PAGE 18
LTC4221 U W U U APPLICATIO S I FOR ATIO The LTC4221 can also be configured to automatically retry after a fault condition. As shown in Figure 10, the FAULT (which has an internal 3.8μA pull-up current source) and both ON pins are connected together. The timing diagram in Figure 11 illustrates a simultaneous start-up sequence where the LTC4221 is powered up into a load overcurrent condition on channel 1.
PAGE 19
LTC4221 U W U U APPLICATIO S I FOR ATIO latch is cleared and the FAULT pin sources a 3.8μA pull-up current to charge up CON1. The typical delay tON is : tON = (0.851V – 0.4V ) • C ON1 3.8μA (3) CURRENT FLOW TO LOAD TRACK WIDTH W: 0.
PAGE 20
LTC4221 U W U U APPLICATIO S I FOR ATIO Timer Function The TIMER pin controls the initial cycle and the channel start-up cycles with an external capacitor, CTIMER. There are two comparator thresholds: VTMR(H) (1.234V) and VTMR(L) (0.4V). In addition, the pin has a 1.9μA pull-up current, a 20μA pull-up current and a N-channel MOSFET pull-down. When the card is being inserted into the bus connector, the long pins mate first which brings up the supplies at time point 1 of Figure 13.
PAGE 21
LTC4221 U W U U APPLICATIO S I FOR ATIO Start-Up Cycle With Current Limit During a channel start-up cycle, if the inrush current as according to Equation (12) is large enough to cause a voltage drop greater than the active current limit threshold (VSENSE(ACL)) across the sense resistor, an internal servo loop controls the operation of the 9.
PAGE 22
LTC4221 U W U U APPLICATIO S I FOR ATIO supply voltages, the LTC4221 can drive any MOSFET rated with 4.5V or 2.5V gate drive. For higher supply voltages up to 13.5V, the LTC4221 can drive any MOSFET rated with a 10V or 4.5V gate drive. The selected MOSFET should fulfill two VGS criteria: 1. Positive VGS absolute maximum rating > LTC4221’s maximum ΔVGATE. 2. Negative VGS absolute maximum rating > supply voltage.
PAGE 23
LTC4221 U W U U APPLICATIO S I FOR ATIO the input supply line, exhibiting a peak overshoot to 2.5 times the steady-state value. This peak is followed by a damped sinusoidal response whose duration and period are dependent on the resonant circuit parameters. This can cause detrimental damage to board components unless measures are taken. The energy stored in the lead/trace inductance is easily controlled with snubbers and/or transient voltage suppressors.
PAGE 24
LTC4221 U W U U APPLICATIO S I FOR ATIO TRACK WIDTH W CURRENT FLOW TO LOAD RSENSE2 CHANNEL 2 INPUT W RX2 R4 CX2 R3 D G D S D S D S CX1 R1 RX1 R2 CHANNEL 2 OUTPUT FILTER 8 RF4 TIMER 9 FAULT 7 GND 10 PWRGD1 PWRGD2 11 6 FB2 12 FB1 5 GATE2 13 GATE1 4 VCC2 15 3 SENSE2 14 VCC1 SENSE1 2 ON1 1 LTC4221* Z1 CHANNEL 1 INPUT CTIMER ON2 16 • • VIAS • • • W RF3 Z2 GND CURRENT FLOW TO LOAD POWER MOSFET SO-8 VIAS • • • • • GND TO LOAD BOTTOM LAYER AND GND TRACE RF2 CFIL
PAGE 25
LTC4221 U APPE DIX Table 2. N-Channel Selection Guide CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER 0 to 2 MMDF3N02HD Dual N-Channel SO-8 RDS(ON) = 0.1Ω, CISS = 455pF ON Semiconductor 2 to 5 MMSF5N02HD Single N-Channel SO-8 RDS(ON) = 0.025Ω, CISS = 1130pF ON Semiconductor 5 to 10 MTB50N06V Single N-Channel DD Pak RDS(ON) = 0.028Ω, CISS = 1570pF ON Semiconductor 10 to 20 MTB75N05HD Single N-Channel DD Pak RDS(ON) = 0.0095Ω, CISS = 2600pF ON Semiconductor Table 3.
PAGE 26
LTC4221 U TYPICAL APPLICATIO S Simultaneous Turn-On with Autoretry Function—Linked Current Limits BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V PCB EDGE CONNECTOR (MALE) LONG RSENSE1 0.004Ω RX1 10Ω LONG VCC2 2.5V Q1 IRF7413 RSENSE2 0.004Ω CX1 100nF Z1 CX2 100nF R3 12.4k R2 16.5k Q2 IRF7413 RX2 10Ω Z2 2 1 VCC1 3 4 15 SENSE1 GATE1 VCC2 14 13 SENSE2 GATE2 FB2 ON1 R1 4.22k RF3 14.3k 12 RF4 5.11k 16 7 LONG GND VOUT1 3.3V 5A VOUT2 2.
PAGE 27
LTC4221 U TYPICAL APPLICATIO S Sequenced Up/Down, Channel 1 Up First, Down Last BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V PCB EDGE CONNECTOR (MALE) LONG RSENSE1 0.004Ω RX1 10Ω LONG VCC2 2.5V RSENSE2 0.004Ω Z1 ON 0V TO 3.3V OR 3.3V TO 0V Q1 IRF7413 Z2 CX1 100nF SHORT R5 13k R3 8.06k R2 6.98k Q2 IRF7413 RX2 10Ω CX2 100nF RF3 14.3k 2 R4 10k D1 1 VCC1 3 4 15 SENSE1 GATE1 VCC2 14 13 SENSE2 GATE2 FB2 ON1 R1 17.8k GND 12 RF4 5.11k 16 FAULT VOUT1 3.3V 5A VOUT2 2.
PAGE 28
LTC4221 U TYPICAL APPLICATIO Sequenced Up/Down, Channel 2 Up First, Down Last BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V PCB EDGE CONNECTOR (MALE) LONG RSENSE1 0.004Ω RX1 10Ω LONG VCC2 2.5V Z1 ON 0V TO 3.3V OR 3.3V TO 0V Q1 IRF7413 RSENSE2 0.004Ω CX1 100nF R6 10k R3 12.1k R2 20.5k R4 23.2k RF3 14.3k VCC1 SENSE1 GATE1 VCC2 SENSE2 GATE2 FB2 ON1 R1 23.7k RF4 5.11k D1 PWRGD2 ON2 LTC4221 SHORT FAULT FAULT LONG GND Q2 IRF7413 RX2 10Ω CX2 100nF Z2 SHORT VOUT1 3.3V 5A VOUT2 2.