Datasheet

LTC4216
15
4216fa
For more information www.linear.com/LTC4216
applicaTions inForMaTion
Figure 8. Normal Power-Up/Power-Down Sequence
capacitors. A second timing cycle starts at time point 11
when the FB pin voltage exceeds 0.6V and the voltage
across the sense resistor drops below 25mV.RESET goes
high at the end of the second timing cycle (time point 12)
when TIMER reaches the V
TMR(TH)
threshold.
SENSEP
ON
TIMER
SS
GATE
V
OUT
RESET
V
CC
POWER GOOD
V
FB
> 0.6V
POWER BAD
V
FB
< 0.6V
(V
GATE
– V
OUT
) > V
GS(TH)
V
TMR(TH)
V
TMR(TH)
TRACKS SS RAMP
20µA
2µA 2µA
0.72V
0.4V
0.8V
10µA
10µA
1µA
1 2 3 4 5 6 7 8 9
CHECK FOR GATE,
FILTER, TIMER,
SS < 0.2V
CHECK FOR GATE, FILTER,
TIMER, SS < 0.2V AND FAULT HIGH
FAULT HIGH
10 11 12 13
PLUG-IN CYCLE
FIRST TIMING CYCLE
POWER-GOOD DELAY
SECOND TIMING CYCLE
4216 F08
START
GATE
RAMP
ELECTRONIC CIRCUIT
BREAKER ARMED
RESET GOES HIGH
IN
RESET
MODE
ON GOES LOW
RESET PULLED LOW
DUE TO POWER BAD
START 2ND TIMING CYCLE
(CHECK TIMER < 0.2V AND
)