Datasheet

LTC4215-1/LTC4215-3
20
421513fc
I
2
C Device Addressing
Nine distinct bus addresses are available using two 3-
state address pins, ADR0 and ADR1. Table 1 shows the
correspondence between pin states and addresses. Note
that address bits B7 and B6 are internally confi gured to
“10”. In addition, the LTC4215-1/LTC4215-3 respond to
two special addresses. Address (1011 111) is a mass
write address that writes to all LTC4215-1/LTC4215-3s,
regardless of their individual address settings. Mass write
can be disabled by setting register bit A4 to zero. Address
(0001 100) is the SMBus Alert Response Address. If the
LTC4215-1/LTC4215-3 are pulling low on the GPIO2 pin due
to an alert, it acknowledges this address by broadcasting
its address and releasing the GPIO2 pin.
APPLICATIONS INFORMATION
Figure 7. LTC4215-1/LTC4215-3 Serial Bus SDA Write Byte Protocol
Figure 8. LTC4215-1/LTC4215-3 Serial Bus SDA Write Word Protocol
Figure 9. LTC4215-1/LTC4215-3 Serial Bus SDA Read Byte Protocol
Figure 10. LTC4215-1/LTC4215-3 Serial Bus SDA Read Word Protocol
Figure 11. LTC4215-1/LTC4215-3 Serial Bus SDA Alert Response Protocol
S ADDRESS
1 0 a4:a0
4215 F07
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
COMMAND DATA
X X X X X b2:b00
W
000b7:b0
A A AP
S ADDRESS
1 0 a4:a0
COMMAND DATA DATA
X X X X X b2:b00
W
000 0
4215 F08
X X X X X X X Xb7:b0
A
A A AP
S ADDRESS
1 0 a4:a0 1 0 a4:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X X b2:b00
W
00
4215 F10
A A A P
S ADDRESS
1 0 a4:a0 1 0 a4:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X X b2:b00
W
00
4215 F11
A
0
A
b7:b0
DATA
A A P
S
ALERT
RESPONSE
ADDRESS
0 0 0 1 1 0 0
DEVICE
ADDRESS
1 0 a4:a0 0 11
R
0
4215 F11
A A
P